Prosecution Insights
Last updated: October 22, 2026
Application No. 18/617,946

ELECTRONIC DEVICE SUPPORTING MANUFACTURE OF SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE

Non-Final OA §101
Filed
Mar 27, 2024
Priority
Sep 19, 2023 — RE 10-2023-0125045
Examiner
KIK, PHALLAKA
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
876 granted / 965 resolved
+22.8% vs TC avg
Minimal +2% lift
Without
With
+1.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
15 currently pending
Career history
979
Total Applications
across all art units

Statute-Specific Performance

§101
32.5%
-7.5% vs TC avg
§103
16.3%
-23.7% vs TC avg
§102
26.5%
-13.5% vs TC avg
§112
9.1%
-30.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 965 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Application filed on 3/17/1014 and IDS filed on 3/27/2024 and 11/01/2024. Claims 1-20 are pending. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-12,20 are rejected under 35 U.S.C. 101 because even though the claimed invention is directed a process and a machine respectively (Step 1, in MPEP 2100 chart); the claims are directed to abstract ideas involving mathematical calculations/algorithms without significantly more (Step 2A, Prong One, in MPEP 2100 chart). The claim(s) recite(s) the judicial exception comprising the steps/operations of inferring a center and a distribution of a skew…using a deep, calculating a loss and training the deep learning module which are all mathematical calculations/algorithms. This judicial exception is not integrated into a practical application because there is no recited practical application (Step 2B, Prong Two in MPEP 2100 chart)--(i.e., the layout image corresponding to the layout data is NOT modified based on the results of the training based on the loss, similar to claim 12—that is, the results of the training is NOT being recited as being used in some way to manufacture or help support the manufacture of the semiconductor device). The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because there is no such recitation. Thus, the claims are NOT directed to eligible under 35 USC 101. Applicant want to add an additional step/operation at the end of claims 1 and 20, --modifying the layout image corresponding to the layout data based on a result of the trained deep learning module using the loss-- similar to claim 12 or alternatively, add an additional step that would somehow affect the manufacturing process of the semiconductor device using the result of the trained deep learning module, to provide for this integrated practical application and place the claims in patent eligible subject matter. Allowable Subject Matter Claims 13-19 are allowed. Claims 1-12,20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action. The following is a statement of reasons for the indication of allowable subject matter: As per claims 1-12,20, the independent claims 1, 20, recite the method/electronic device for (support) manufacture of a semiconductor device comprising a combination of inventive steps/operations/instructions comprising inferring a center and a distribution of a skew of each of patterns of the layout data, edges of the layout data, or both patterns and edges of the layout data, based on the layout data and the feature data using deep learning module; calculating a loss based on the center and the distribution of the skew and the skew data; and training the deep learning module based on the loss, as claimed, which the prior arts made of record failed to teach or suggest as claimed. As per claims 13-19, the independent claim 13, from which the respective claims depend, recites the operating method of an electronic device which includes an processor and is configured to support manufacture of a semiconductor device comprising a combination of inventive steps/operations comprising inferring a center and a distribution of a skew of each of patterns or edges of the layout data based on the layout data and the feature data, by using a deep learning module; performing Monte Carlo simulation based on the center of the skew and on the distribution of the skew; and modifying a layout image corresponding to the layout data based on a result of the Monte Carlo simulation, as claimed, which the prior arts made of record failed to teach or suggest as claimed. Furthermore, under the 2019 Patent Eligibility Guideline, the claims are directed to patent eligible subject matter because (1) under Step 1, the claims are directed to a process; (2) under Step 2A,Prong One, the claims recite abstract ideas involving mathematical concepts comprising mathematical relationships, mathematical formulas or equations, and mathematical calculations in the steps/operations of inferring, performing Monte Carlo simulation; (3) under Step 2B, Prong Two, the claims recited integrated practical application involving the step of modifying the layout image corresponding the layout data based on the Monte Carlo simulation, which would directly/indirectly affect the manufacture of semiconductor device as known in the art; thus resulting in significantly more than the judicial exception (see MPEP 2106). Additionally, the claims are NOT directed to a mental process since one of ordinary skilled in the art at the time of the filing of the invention, would NOT reasonably be able to perform the method mentally since the calculations would involve large amount of data associated with the electronic design, as normally found in the art of computer-aided design and analysis of circuits and semiconductor mask; nor are the claims directed to certain methods of organizing human activity. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri, 8:30AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 5712727483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Any response to this action should be mailed to: Commissioner for Patents P. O. Box 1450 Alexandria, VA 22313-1450 or faxed to: 571-273-8300 /PHALLAKA KIK/Primary Examiner, Art Unit 2851 September 23, 2026
Read full office action

Prosecution Timeline

Mar 27, 2024
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §101
Oct 13, 2026
Applicant Interview (Telephonic)
Oct 13, 2026
Examiner Interview Summary

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
92%
With Interview (+1.6%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 965 resolved cases by this examiner. Grant probability derived from career allowance rate.

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