DETAILED ACTION
This application, 18/416151, attorney docket AD9667-US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The applicant or assignee is IDEMITSU KOSAN CO., LTD., and claims foreign priority to 2023-050864, filed 03/28/2023. Applicant’s election of Claim Group I, namely, claims 1-12, without traverse in the reply filed on 9/4/2026 is acknowledged. Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claims 1-12 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 8 and 12 are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Ito et al. (U.S. 2016/0372606).
As for claim 1,
Ito teaches in figures 1A, 1B and 1C, semiconductor device comprising:
a metal oxide layer (123, [0136]) on an insulating surface (110);
an oxide semiconductor layer (122) on the metal oxide layer;
a gate insulating layer (150) on the oxide semiconductor layer; and
a gate wiring (160) on the gate insulating layer;
wherein the metal oxide layer has a first region overlapping the gate wiring and the oxide semiconductor layer (center fig 1B),
a second region (left and right of center fig 1B) overlapping the oxide semiconductor layer and not overlapping the gate wiring, and
a third region (left of center fig 1C) overlapping the gate wiring and not overlapping the oxide semiconductor layer.
As for claim 2,
Ito teaches the semiconductor device according to claim 1, and teaches that the metal oxide layer has the same pattern shape as the sum set of the pattern shapes of the gate wiring and the oxide semiconductor layer in a plan view. (shown in plan view, where no ghost lines are shown to represent offset edges between gate and semiconductor.)
As for claim 3,
Ito teaches semiconductor device according to claim 1, wherein the gate insulating layer has the same pattern shape as the gate wiring in a plan view. (shown in plan view, where no ghost lines are shown to represent offset edges between gate and gate insulator.)
As for claim 4.
Ito teaches the semiconductor device according to claim 1, further comprising:
an insulating layer (180) on the gate wiring,
wherein the first region does not contact the insulating layer ( the oxide layer is completely covered and surrounded by the gate and semiconductor) , and a side surface of the second region and a side surface of the third 56 region are in contact with the insulating layer.
As for claim 5,
Ito teaches the semiconductor device according to claim 4, wherein the insulating layer contacts the gate wiring, the gate insulating layer and the oxide semiconductor layer (shown in figs 1b and 1c at the element sidewalls.)
As for claim 8,
Ito teaches the semiconductor device according to claim 1 and teaches that the first region contacts a channel region, and the second region contacts a source region or a drain region (195).
As for claim 12,
Ito teaches the device of claim 1 and teaches that the device controls a pixel that is part of a display device comprising a plurality of pixels [0540-0545].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ito in view of Ishihara et al. (U.S. 2015/0084043)
As for claim 6,
Ito teaches the semiconductor device according to claim 4, but does not teach that the insulating layer has a stacked structure including a silicon nitride layer and a silicon oxide layer.
However, Ishihara teaches in figure 1B, an insulating layer (112/114/116) has a stacked structure including a silicon nitride layer (116) and a silicon oxide layer. (112/115).
It would have been obvious to one skilled in the art at the effective filing date of this application use and oxide/nitride stack because the oxide relieves damage to the metal oxide layer (Ishihara [0101]), and the nitride prevents oxygen outward diffusion. (Ishihara [0109]). One skilled in the art would have combined these elements with a reasonable expectation of success.
Claims 7 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ito
As for claim 7,
Ito teaches the semiconductor device according to claim 1, and teaches that the oxide semiconductor layer contains at least two or more metallic elements including indium [0171-0172]), but does not teach that a ratio of indium to the at least two or more metallic elements is 50% or more.
However, the metallic ratio of elements is a result-dependent variable that controls the properties of the layer such as capacitance, ductility and compatibility with the semiconductor layer. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Because the general conditions are disclosed in the prior art it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller. 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Here one skilled would optimize the metallic element ratio to meet the needs of the device through routine experimentation, and the applicant does not disclose any unexpected result using the claimed ratio, so the ratio is would have been obvious to one of ordinary skill in the art.
As for claim 9,
Ito teaches the semiconductor device according to claim 8 and teaches the channel region and the source region or the drain region are continuous in a first direction (across the page in figure 1B), Ito shows an overlap of the s/d with the gate insulator in figure 1B but is silent on a width in the first direction of a portion of the source region or the drain region in contact with the gate insulating layer is 1 um or less.
However, the width of the contact portion is a result dependent variable that controls the channel length and therefore the threshold voltage, and the overlap would be found through ordinary experimentation, so obvious to one skilled in the art.
As for claim 10,
Ito makes obvious the semiconductor device according to claim 9, but is silent on a width of the gate wiring in the first direction is 4 um or less. However, the width of the gate is a result dependent variable that controls the channel length and therefore the threshold voltage, so a gate wiring width of 4um or less would be found through ordinary experimentation, and be obvious to one skilled in the art.
As for claim 11,
Ito makes obvious the semiconductor device according to claim 9, but is silent on a width of the gate wiring in the first direction is 1 pm or more and greater than twice a width in the first direction of the portion of the source region or the drain region in contact with the gate insulating layer.
However the dimension of the gate wiring relative to the source drain is a result dependent variable that controls the threshold voltage, so the claimed width would be found through ordinary experimentation, and be obvious to one skilled in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893
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