DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-26 in the reply filed on 07/24/2026 is acknowledged.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date.
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 17/469,281 & 18/479,511 and the foreign (Korean) parent KR10-2021-0031082, fail to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The above documents fail to provide sufficient support for the limitation “heat dissipation layer”. As such, the instant application is not entitled to the priority date of the US parent application (‘281, ‘511) and the foreign priority date set by the Korean parent ‘082.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18 & 20-26 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 2025/0062287) in view of CHUNG et al. (US Pub. 2025/0096215).
Regarding claim 16, Lee teaches a stack package comprising:
semiconductor dies (CS2 and/or CS1) offset stacked (Fig. 7);
an encapsulant layer encapsulating the semiconductor dies (CS2 and/or CS1);
redistribution layers 76 formed on the encapsulant layer 54 (Fig. 7); and
vertical connectors (46, 50, 32 & 22) penetrating the encapsulant layer 54 and connecting the semiconductor dies (CS2 and/or CS1) to the redistribution layers 76 (Fig. 7).
Lee is silent on the semiconductor dies positioned on a heat dissipation layer and the encapsulant layer coupled to the heat dissipation layer. However, CHUNG teaches in Fig. 1 semiconductor dies 190 positioned on a heat dissipation layer 165 and an encapsulant 197 coupled to the heat dissipation layer 165. This has the advantage of lowering operating temperatures to maintain high performance, extend lifespan and prevent hardware failures. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee with the heat dissipation layer, as taught by CHUNG, so as to obtain an improved semiconductor device.
Regarding claim 17, the combination of Lee and CHUNG teaches the stack package of claim 16, wherein the heat dissipation layer 165 includes a metal film, an alloy film, or a metal film with a plating layer or a laminated film including different metal films bonded together (CHUNG’s Fig. 1 & Para [0074]).
Regarding claim 18, the combination of Lee and CHUNG teaches the stack package of claim 16, wherein the heat dissipation layer comprises copper or nickel (CHUNG’s Fig. 1 & Para [0074]).
Regarding claim 20, the combination of Lee and CHUNG teaches the stack package of claim 16, wherein the semiconductor dies include: a lower semiconductor die (e.g. 12); a first intermediate semiconductor die (e.g. 16 or 40) stacked on the lower semiconductor die with a first offset; and an upper semiconductor die (e.g. 18 or 42) stacked on the first intermediate semiconductor die with a second offset in an opposite direction to the first offset (Lee’s Fig. 7 & CHUNG’s Fig. 1).
Regarding claim 21, the combination of Lee and CHUNG teaches the stack package of claim 20, further comprising an adhesive layer attaching the lower semiconductor die (lowest 192 close to 165) to the heat dissipation layer 165 (CHUNG’s Fig. 1 & Para [0114]).
Regarding claim 22, the combination of Lee and CHUNG teaches the stack package of claim 20, wherein the semiconductor dies further include a second intermediate semiconductor die 14 stacked between the lower semiconductor die 12 and the first intermediate semiconductor die 16 with a third offset in substantially the same direction as the first offset (Lee’s Fig. 7).
Regarding claim 23, the combination of Lee and CHUNG teaches the stack package of claim 22, wherein the upper semiconductor die is positioned to expose a portion of the second intermediate semiconductor die while exposing a portion of the first intermediate semiconductor die (Lee’s Fig. 7).
Regarding claim 24, the combination of Lee and CHUNG teaches the stack package of claim 20, wherein the vertical connectors include: a first bonding wire 22 connected to the lower semiconductor die 12 and extending substantially vertically past the upper semiconductor die (18 or 42) and the first intermediate semiconductor die (16 or 40); and a second bonding wire (32 or 50) connected to the first intermediate semiconductor die (16 or 40) and extending substantially vertically past the upper semiconductor die (18 or 42, see Lee’s Fig. 7).
Regarding claim 25, the combination of Lee and CHUNG teaches the stack package of claim 24, wherein the first bonding wire 22 and the second bonding wire (32 50) are formed at positions opposite to each other with the upper semiconductor die (18 or 42) interposed therebetween (see Lee’s Fig. 7). 112b
Regarding claim 26, the combination of Lee and CHUNG teaches the stack package of claim 24, wherein the vertical connectors further include conductive bumps (e.g. pads CP4) connected to the upper semiconductor die 18 (Lee’s Fig. 7).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee and CHUNG as applied to claim16 above, and further in view of Ng et al. (US Pub. 2021/0066883).
Regarding claim 19, the combination of Lee and CHUNG is the stack package of claim 16, wherein the heat dissipation layer includes a cavity into which a lower semiconductor die among the stacked semiconductor dies is disposed. However, Ng teaches in Fig. 3, wherein a heat dissipation layer 340 includes a cavity (note cavity/opening in 340) into which a semiconductor die 2 is disposed. This has the advantages of accommodating semiconductor components to save precious real estate within the semiconductor device. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to modify the invention of Lee and CHUNG with the heat dissipation layer, as taught by Ng, so as to further scale and save precious space in a semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOR KARIMY whose telephone number is (571)272-9006. The examiner can normally be reached Monday - Friday: 8:30 AM -5:00 PM.
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/TIMOR KARIMY/Primary Examiner, Art Unit 2818
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