DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed April 27, 2026.
Claims 1-20 are pending. Claims 1, 8-9, 11, 13 and 18-20 are amended. Claims 1, 13 and 20 are independent.
Continued Examination Under 37 CFR 1.114 After Final Rejection
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 27, 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on May 3, 2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 8, 11, 13-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Srinath et al. (U.S. 6,191,644; hereinafter “Srinath”) in view of Xiao et al. (CN 114253339; hereinafter “Xiao”).
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Regarding independent claim 1, Srinath teaches a start-up circuit for bandgap reference (BGR) generation (see Examiner’s Markup Srinath’s Figure 2), comprising:
a start-up capacitor (Fig. 2: 60) connected to a bandgap voltage (VBG) node (see Examiner’s Markup Srinath’s Figure 2) of a BGR sub-circuit (Fig. 2: 10), the start-up capacitor (Fig. 2: 60) configured to determine whether an operating state of the BGR sub-circuit is in a normal state or a failure state (“brief power-down and power-up sequence event, and the absence of a power-up pulse on line RID,” see col. 7, ll. 44-59); and
an output transistor (Fig. 2: 70) connected to a first node of the BGR sub-circuit (Fig. 2: NBIAS), the output transistor is configured to charge the first node to change the operating state of the BGR sub-circuit to the normal state, in response to the operating state of the BGR sub-circuit being in the failure state (see Abstract).
However, Srinath is silent with respect to the BGR sub-circuit configured to output a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state.
Similar to Srinath, Xiao teaches a circuit bandgap reference (BGR) generation (see description of the band-gap reference voltage source module 200).
Furthermore, Xiao teaches a BGR sub-circuit configured to output a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state (see description of the band-gap reference voltage source module 200).
Since Xiao and Srinath are from the same field of endeavor, the teachings described by Xiao would have been recognized in the pertinent art of Srinath.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao with the teachings of Srinath for the purpose of ensuring continuous output of the band-gap reference voltage while reducing working time of the band-gap reference voltage source, see Xiao’s description of the band-gap reference voltage source module 200 and Figure 1.
Regarding claim 2, Srinath in combination with Xiao teaches the limitations with respect to claim 1.
As discussed above, Srinath’s capacitor action-based start-up circuit in combination with Xiao is substantially identical in structure to the claimed “capacitor action-based start-up circuit,” where the differences reside only in the remaining limitations relating to function of “wherein the first node is a slowest node of the BGR sub-circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Srinath’s capacitor action-based start-up circuit in combination with Xiao appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 3, Srinath in combination with Xiao teaches the limitations with respect to claim 1.
Furthermore, Srinath teaches wherein the output transistor is further configured to:
turn off while the operating state of the BGR sub-circuit is in the normal state (see col. 6, ll. 57-67 and col. 7, ll. 1-2); and
charge the first node of the BGR sub-circuit in response to the operating state of the BGR sub-circuit being in the failure state (apply precharged power supply voltage to node NBIAS, even in the absence of an active high pulse on line RID, see col. 6, ll. 3-19).
Regarding claim 4, Srinath in combination with Xiao teaches the limitations with respect to claim 1.
Furthermore, Srinath teaches wherein the start-up capacitor is further configured to:
maintain a voltage differential between a top plate and a bottom plate of the start-up capacitor in response to the operating state of the BGR sub-circuit being the failure state, wherein the voltage differential facilitates activation of the output transistor (see col. 6, ll. 3-19).
Regarding claim 8, Srinath in combination with Xiao teaches the limitations with respect to claim 1.
Furthermore, Srinath teaches wherein the capacitor action-based start-up circuit further comprises:
an auxiliary network (Fig. 2: 42p, 44p, 52p and 54p) including an auxiliary transistor (Fig. 2: 52p/54p), the auxiliary network configured to control activation and deactivation of the start-up circuit (see col. 3, ll. 44-62 and col. 4, ll. 11-23); and
the auxiliary transistor configured to control a timing of the start-up circuit activation (see col. 3, ll. 44-62 and col. 4, ll. 11-23).
Regarding claim 11, Srinath in combination with Xiao teaches the limitations with respect to claim 1.
As discussed above, Srinath’s capacitor action-based start-up circuit in combination with Xiao is substantially identical in structure to the claimed “capacitor action-based start-up circuit,” where the differences reside only in the remaining limitations relating to function of “wherein an operating state of the start-up circuit is determined by a voltage of the VBG node of the BGR sub-circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Srinath’s capacitor action-based start-up circuit in combination with Xiao appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding independent claim 13, Srinath teaches a system (Fig. 2), comprising:
a bandgap reference (BGR) sub-circuit (Fig. 2: 10); and
a start-up circuit configured to generate a BGR voltage (see Examiner’s Markup Srinath’s Figure 2), wherein the start-up circuit comprises,
a start-up capacitor (Fig. 2: 60) connected to a bandgap voltage (VBG) node (see Examiner’s Markup Srinath’s Figure 2) of the BGR sub-circuit (Fig. 2: 10), the start-up capacitor configured to determine whether an operating state of the BGR sub-circuit is in a normal state or a failure state (“brief power-down and power-up sequence event, and the absence of a power-up pulse on line RID,” see col. 7, ll. 44-59); and
an output transistor (Fig. 2: 70) connected to a first node of the BGR sub-circuit (Fig. 2: NBIAS), the output transistor configured to charge the first node to change the operating state of the BGR sub-circuit to the normal state, in response to the operating state of the BGR sub-circuit being the failure state (see Abstract).
However, Srinath is silent with respect to the BGR sub-circuit configured to output a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state.
Similar to Srinath, Xiao teaches a bandgap reference (BGR) sub-circuit (see description of the band-gap reference voltage source module 200).
Furthermore, Xiao teaches the BGR sub-circuit configured to output a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state (see description of the band-gap reference voltage source module 200).
Since Xiao and Srinath are from the same field of endeavor, the teachings described by Xiao would have been recognized in the pertinent art of Srinath.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao with the teachings of Srinath for the purpose of ensuring continuous output of the band-gap reference voltage while reducing working time of the band-gap reference voltage source, see Xiao’s description of the band-gap reference voltage source module 200 and Figure 1.
Regarding claim 14, Srinath in combination with Xiao teaches the limitations with respect to claim 13.
As discussed above, Srinath’s system in combination with Xiao is substantially identical in structure to the claimed “system,” where the differences reside only in the remaining limitations relating to function of “wherein the first node is a slowest node of the BGR sub-circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Srinath’s system in combination with Xiao appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 15, Srinath in combination with Xiao teaches the limitations with respect to claim 13.
Furthermore, Srinath teaches wherein the output transistor is further configured to:
turn off while the operating state of the BGR sub-circuit is in the normal state (see col. 6, ll. 57-67 and col. 7, ll. 1-2); and
charge the first node of the BGR sub-circuit in response to the operating state of the BGR sub-circuit being in the failure state (apply precharged power supply voltage to node NBIAS, even in the absence of an active high pulse on line RID, see col. 6, ll. 3-19).
Regarding claim 16, Srinath in combination with Xiao teaches the limitations with respect to claim 13.
Furthermore, Srinath teaches wherein the start-up capacitor is further configured to:
maintain a voltage differential between a top plate and a bottom plate of the start-up capacitor in response to the operating state of the BGR sub-circuit being the failure state, wherein the voltage differential facilitates activation of the output transistor (see col. 6, ll. 3-19).
Regarding claim 18, Srinath in combination with Xiao teaches the limitations with respect to claim 13.
Furthermore, Srinath teaches wherein the capacitor action-based start-up circuit further comprises:
an auxiliary network (Fig. 2: 42p, 44p, 52p and 54p) including an auxiliary transistor (Fig. 2: 52p/54p), the auxiliary network configured to control activation and deactivation of the start-up circuit (see col. 3, ll. 44-62 and col. 4, ll. 11-23); and
the auxiliary transistor configured to control a timing of the start-up circuit activation (see col. 3, ll. 44-62 and col. 4, ll. 11-23).
Regarding claim 19, Srinath in combination with Xiao teaches the limitations with respect to claim 13.
As discussed above, Srinath’s system in combination with Xiao is substantially identical in structure to the claimed “system,” where the differences reside only in the remaining limitations relating to function of “wherein an operating state of the start-up circuit is determined by a voltage of the VBG node of the BGR sub-circuit.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Srinath’s system in combination with Xiao appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding independent claim 20, Srinath teaches a method of operating a start-up circuit (see Examiner’s Markup Srinath’s Figure 2), the method comprising:
determining, using a start-up capacitor (Fig. 2: 60), whether an operating state of a bandgap reference (BGR) sub-circuit (Fig. 2: 10) is in a normal state or a failure state (“brief power-down and power-up sequence event, and the absence of a power-up pulse on line RID,” see col. 7, ll. 44-59), the start-up capacitor connected to a bandgap voltage (VBG) node (see Examiner’s Markup Srinath’s Figure 2) of the BGR sub-circuit (Fig. 2: 10);
turning off an output transistor (Fig. 2: 70), while the operating state of the BGR sub-circuit is in the normal state (see col. 6, ll. 57-67 and col. 7, ll. 1-2), the output transistor connected to a first node of the BGR sub-circuit (Fig. 2: NBIAS); and
charging, using the output transistor, the first node of the BGR sub-circuit in response to the operating state of the BGR sub-circuit being in the failure state (apply precharged power supply voltage to node NBIAS, even in the absence of an active high pulse on line RID, see col. 6, ll. 3-19).
However, Srinath is silent with respect to outputting, using the BGR sub-circuit, a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state.
Similar to Srinath, Xiao teaches a bandgap reference (BGR) sub-circuit (see description of the band-gap reference voltage source module 200).
Furthermore, Xiao teaches the step of outputting, using the BGR sub-circuit, a reference signal to the VBG node in response to the BGR sub-circuit being in the normal state (see description of the band-gap reference voltage source module 200).
Since Xiao and Srinath are from the same field of endeavor, the teachings described by Xiao would have been recognized in the pertinent art of Srinath.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Xiao with the teachings of Srinath for the purpose of ensuring continuous output of the band-gap reference voltage while reducing working time of the band-gap reference voltage source, see Xiao’s description of the band-gap reference voltage source module 200 and Figure 1.
Allowable Subject Matter
Claims 5-7, 9-10, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 5, there is no teaching or suggestion in the prior art of record to provide the recited the operating state of the BGR sub-circuit being the normal state the top plate of the start-up capacitor is configured to be charged to VDD-VTHDIODE the bottom plate of the start-up capacitor is configured to be charged to a voltage of the VBG node the start-up circuit is configured to be in an OFF state and the output transistor is configured to be turned off.
With respect to claim 6, there is no teaching or suggestion in the prior art of record to provide the recited the operating state of the BGR sub-circuit being the failure state, the output transistor is further configured to be switched on in response to the top plate of the start-up capacitor being charged to VDD-VTHDIODE- the voltage differential, the bottom plate of the start-up capacitor is further configured to be charged to a difference between a voltage of the VBG node and the voltage differential, and the start-up circuit is further configured to be turned on and change a condition of a memory node to be |VTHMOS| > VTHDIODE.
With respect to claim 7, there is no teaching or suggestion in the prior art of record to provide the recited transition from 1.2V in response to the operating state of the BGR sub-circuit being the normal state, to VTHDIODE in response to the operating state of the BGR sub-circuit being the failure state, wherein the VTHDIODE varies between 0.5V to 0.7V.
With respect to claim 9, there is no teaching or suggestion in the prior art of record to provide the recited failsafe mechanism including a failsafe transistor, the failsafe mechanism configured to protect the auxiliary network from false charging during one or more failure conditions while the BGR sub-circuit is powering up.
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited delay deactivation of the auxiliary transistor to facilitate a proper charging of the start-up capacitor to VDD-VTHDiode voltage.
With respect to claim 12, there is no teaching or suggestion in the prior art of record to provide the recited start-up circuit comprises a diode, the diode configured to decrease a probability of zero reverse current, an auxiliary transistor configured to be switched off in response to the start-up circuit being activated, and a top plate of the start-up capacitor is configured to charge to VDD-VTHDiode a single time in response to the start-up circuit being activated.
With respect to claim 17, there is no teaching or suggestion in the prior art of record to provide the recited the operating state of the BGR sub-circuit being the failure state, the output transistor is further configured to be switched on in response to the top plate of the start-up capacitor being charged to VDD-VTHDIODE- the voltage differential, the bottom plate of the start-up capacitor is further configured to be charged to a difference between a voltage of the VBG node and the voltage differential, and the start-up circuit is further configured to be turned on and change a condition of a memory node to be |VTHMOS| > VTHDIODE.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 8, 11, 13-16 and 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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