Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18618469 filed on 03/27/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Election/Restrictions
Applicant’s election with traverse of claims 1-16, 18-20 in the reply filed on 5/12/2026 is acknowledged.
Applicant’s argument with respect to species V and VI is persuasive, accordingly, species V and VI are considered as one species.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (US 2022/0199521) in view of Tomita (US 2012/0261835).
Regarding Independent claim 1, Lanzillo et al. teach a semiconductor device comprising:
a transistor structure (Figs. 1 & 2B, element 108, paragraph 0023);
one or more 1.sup.st metal lines (Figs. 1 & 2B, element 134, paragraph 0024) above the transistor structure; and
one or more 1.sup.st vias (Figs. 1 & 2B, element 138, paragraph 0024) formed on respective 1.sup.st metal lines among the one or more 1.sup.st metal lines;
a 2.sup.nd via (Figs. 1 & 2A, element 148, paragraph 0027) formed on a 1.sup.st via among the one or more 1.sup.st vias; and
a 2.sup.nd metal line (Figs. 1 & 2B, element 136, paragraph 0024) on the 2.sup.nd via,
wherein the one or more 1.sup.st metal lines are arranged in a 1.sup.st direction and extended in a 2.sup.nd direction which intersects the 1.sup.st direction, and the 2.sup.nd metal line is extended in the 1.sup.st direction (Figs. 1-2B).
Lanzillo et al. do not explicitly disclose wherein the one or more 1.sup.st vias comprise at least one dummy via which is not connected to any metal line there above other than an underlying 1.sup.st metal line among the respective 1.sup.st metal lines.
Tomita teach a semiconductor device comprising wherein the one or more 1.sup.st vias (Fig. 1, element 124 & 125, paragraph 0057) comprise at least one dummy via (Fig. 1, element 124, paragraph 0057) which is not connected to any metal line there above other than an underlying 1.sup.st metal line (Fig. 1, element 111, paragraph 0056) among the respective 1.sup.st metal lines.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Lanzillo et al. according to the teachings of Tomita with the motivation to provide reduction in resistance of an interconnecting structure (paragraph 0009).
Regarding claim 2, Lanzillo et al. modified by Tomita teach wherein each of the one or more 1.sup.st vias and each of the respective 1.sup.st metal lines do not have a connection surface, boundary or interface therebetween (Figs. 1 & 2B of Lanzillo).
Regarding claim 3, Lanzillo et al. modified by Tomita teach wherein the 2.sup.nd metal line (Fig. 1, element 171, paragraph 0066 of Tomita) and the 2.sup.nd via (Fig. 1, element 164, paragraph 0063 of Tomita) have a connection surface, boundary or interface therebetween.
Regarding claim 4, Lanzillo et al. modified by Tomita teach wherein the 1.sup.st metal line and the 1.sup.st via are formed of at least one of ruthenium (Ru), molybdenum (Mo) and cobalt (Co), and wherein the 2.sup.nd metal line and the 2.sup.nd via are formed of at least one of copper (Cu), aluminum (Al) and tungsten (W) (paragraph 0035 of Lanzillo).
Regarding claim 5, Lanzillo et al. modified by Tomita teach wherein the 2.sup.nd via and the 2.sup.nd metal line do not have a connection surface, boundary or interface therebetween (Figs. 1 & 2B of Lanzillo).
Regarding claim 6, Lanzillo et al. modified by Tomita teach wherein a height of the at least one dummy via is the same as a height of the 1.sup.st via in a 3.sup.rd direction intersecting the 1.sup.st and 2.sup.nd directions (Fig. 1 of Tomita).
Regarding claim 7, Lanzillo et al. modified by Tomita teach wherein one or more dummy vias comprising the at least one dummy via are not connected to any metal lines thereabove, wherein a height of the one or more dummy vias is the same as the height of the 1.sup.st via in the 3.sup.rd direction (Fig. 1 of Tomita).
Regarding claim 8, Lanzillo et al. modified by Tomita teach wherein a 1.sup.st metal line among the one or more 1.sup.st metal lines which is adjacent, in the 1.sup.st direction, to another 1.sup.st metal line among the one or more 1.sup.st metal lines, on which the 1.sup.st via is formed, does not have a dummy via below the 2.sup.nd metal line (Figs. 1 & 2B of Lanzillo and Fig. 1 of Tomita).
Regarding claim 9, Lanzillo et al. modified by Tomita teach wherein each of the one or more 1.sup.st vias and each of the respective 1.sup.st metal lines do not have a connection surface, boundary or interface therebetween (Figs. 1-2B of Lanzillo).
Regarding claim 10, Lanzillo et al. modified by Tomita teach wherein a length of the 2.sup.nd via is greater than a length of the 1.sup.st via in the 1.sup.st direction, and a width of the 2.sup.nd via is smaller than a width of the 1.sup.st via in the 2.sup.nd direction (paragraph 0071 of Tomita teach a range of width for a via and paragraph 0027 of Lanzillo teach the via length can be varied . Accordingly, the length and width of the vias are art recognized variables. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the length and width of the vias and arrive at the claimed limitations. Furthermore, the applicant has not presented persuasive evidence that the claimed length and width is for a particular purpose that is critical to the overall claimed invention).
Regarding Independent claim 16, Lanzillo et al. teach a semiconductor device comprising:
a transistor structure (Figs. 1 & 2B, element 108, paragraph 0023); and
one or more 1.sup.st metal lines (Figs. 1 & 2B, element 134, paragraph 0024) above the transistor structure, the one or more 1.sup.st metal lines being arranged in a 1.sup.st direction and extended in a 2.sup.nd direction which intersects the 1.sup.st direction;
one or more 1.sup.st vias (Figs. 1 & 2B, element 138, paragraph 0024) on respective 1.sup.st metal lines among the one or more 1.sup.st metal lines; and
one or more 2.sup.nd metal lines (Figs. 1 & 2B, element 136, paragraph 0024) above the one or more 1.sup.st vias, the one or more 2.sup.nd metal lines being arranged in the 2.sup.nd direction and extended in the 1.sup.st direction,
wherein the one or more 1.sup.st vias comprise:
a 1.sup.st via (Figs. 1 & 2B, element 138, paragraph 0024) connected to a 2.sup.nd metal line among the one or more 2.sup.nd metal lines; and
wherein the one or more 1.sup.st vias are arranged in the 1.sup.st direction at a 1.sup.st pitch (Figs. 1-2B).
Lanzillo et al. do not explicitly disclose one or more dummy vias not connected to any of the one or more 2.sup.nd metal lines.
Tomita teach a semiconductor device comprising wherein the one or more 1.sup.st vias (Fig. 1, element 124 & 125, paragraph 0057) comprise at least one dummy via (Fig. 1, element 124, paragraph 0057) which is not connected to any of the one or more 2.sup.nd metal lines.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Lanzillo et al. according to the teachings of Tomita with the motivation to provide reduction in resistance of an interconnecting structure (paragraph 0009).
Regarding claim 18, Lanzillo et al. modified by Tomita teach wherein the one or more 1.sup.st vias are arranged in the 2.sup.nd direction at a 2.sup.nd pitch (Figs. 1-2B of Lanzillo).
Regarding claim 19, Lanzillo et al. modified by Tomita teach wherein the one or more 1.sup.st vias have a same height in a 3.sup.rd direction intersection the 1.sup.st and 2.sup.nd directions (Figs. 1-2B of Lanzillo and Fig. 1 of Tomita).
Regarding claim 20, Lanzillo et al. modified by Tomita teach further comprising a 2.sup.nd via (Figs. 1 & 2A, element 148, paragraph 0027) on a 2.sup.nd metal line (Figs. 1 & 2B, element 136, paragraph 0024) among the one or more 2.sup.nd metal lines, wherein a length of the 2.sup.nd via is greater than a length of the 1.sup.st via in the 1.sup.st direction, and a width of the 2.sup.nd via is smaller than a width of the I′ via in the 2.sup.nd direction (paragraph 0071 of Tomita teach a range of width for a via and paragraph 0027 of Lanzillo teach the via length can be varied . Accordingly, the length and width of the vias are art recognized variables. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the length and width of the vias and arrive at the claimed limitations. Furthermore, the applicant has not presented persuasive evidence that the claimed length and width is for a particular purpose that is critical to the overall claimed invention).
Claims 11-12, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (US 2022/0199521) in view of Pan et al. (US 2022/0359376).
Regarding Independent claim 11, Lanzillo et al. teach a semiconductor device comprising:
a transistor structure (Figs. 1 & 2B, element 108, paragraph 0023);
a 1.sup.st metal line (Figs. 1 & 2B, element 134, paragraph 0024) on the transistor structure;
a 1.sup.st via (Figs. 1 & 2B, element 138, paragraph 0024) on the 1.sup.st metal line;
a 1.sup.st isolation layer (Figs. 1 & 2B, element 144, paragraph 0026) surrounding the 1.sup.st metal line and the 1.sup.st via;
a 2.sup.nd via (Figs. 1 & 2A, element 148, paragraph 0027) on the 1.sup.st via;
a 2.sup.nd metal line (Figs. 1 & 2B, element 136, paragraph 0024) on the 2.sup.nd via; and
a 2.sup.nd isolation layer (Figs. 1 & 2B, element 140, paragraph 0024) surrounding the 2.sup.nd via,
wherein the 1.sup.st metal line and the 1.sup.st via does not have a connection surface, boundary or interface therebetween (Figs. 1 & 2B).
Lanzillo et al. do not explicitly discloses wherein a diffusion barrier layer is formed between the 2.sup.nd via and the 2.sup.nd isolation layer, and wherein a diffusion barrier layer is not formed between the 1.sup.st via and the 1.sup.st isolation layer.
Pan et al. disclose a semiconductor device comprising a diffusion barrier layer (Fig. 23, element 151A, paragraph 0067) is formed between the 2.sup.nd via (Fig. 23, element 146A, paragraph 0067) and the 2.sup.nd isolation layer (Fig. 23, element 160A, paragraph 0067), and wherein a diffusion barrier layer is not formed between the 1.sup.st via (Fig. 23, element 74, paragraph 0021) and the 1.sup.st isolation layer (Fig. 23, element 78, paragraph 0019).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Lanzillo et al. according to the teachings of Pan et al. with the motivation to increase production efficiency and lower associated costs (paragraph 0002).
Regarding claim 12, Lanzillo et al. modified by Pan et al. teach further comprising a 3.sup.rd isolation layer (Fig. 1, element 120, paragraph 0023 of Lanzillo) surrounding the 2.sup.nd metal line.
Regarding claim 14, Lanzillo et al. modified by Pan et al. teach wherein the 1.sup.st metal line and the 1.sup.st via do not have a connection surface, boundary or interface therebetween (Figs. 1 & 2B of Lanzillo).
Regarding claim 15, Lanzillo et al. modified by Pan et al. teach wherein the 1.sup.st metal line and the 1.sup.st via are formed of at least one of ruthenium (Ru), molybdenum (Mo) and cobalt (Co) (paragraph 0035 of Lanzillo).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lanzillo et al. (US 2022/0199521) in view of Pan et al. (US 2022/0359376) and further in view of Tomita (US 2012/0261835).
Regarding claim 13, Lanzillo et al. modified by Pan et al. teach one or more 1.sup.st metal lines comprising the 1.sup.st metal line, the one or more 1.sup.st metal lines being arranged in a 1.sup.st direction and extended in a 2.sup.nd direction which intersects the 1.sup.st direction (Figs. 1-2B of Lanzillo); and one or more 2.sup.nd metal lines comprising the 2.sup.nd metal line, and arranged in the 2.sup.nd direction and extended in the 1.sup.st direction (Figs. 1-2B of Lanzillo).
Lanzillo et al. modified by Pan et al. do not explicitly disclose one or more 1.sup.st vias on respective 1.sup.st metal lines among the one or more 1.sup.st metal lines, the one or more 1.sup.st vias comprising the 1.sup.st via and a dummy via having a same height; wherein the dummy via is not connected to any of the 2.sup.nd metal lines.
Tomita teach a semiconductor device comprising wherein the one or more 1.sup.st vias (Fig. 1, element 124 & 125, paragraph 0057) comprise at least one dummy via (Fig. 1, element 124, paragraph 0057) wherein the dummy via is not connected to any of the 2.sup.nd metal lines (Fig. 1, element 111, paragraph 0056).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Lanzillo et al. according to the teachings of Tomita with the motivation to provide reduction in resistance of a interconnecting structure (paragraph 0009).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
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/SHAHED AHMED/
Primary Examiner, Art Unit 2813
Prosecution Insights