Prosecution Insights
Last updated: August 18, 2026
Application No. 18/618,559

VECTOR TEST ZONED INSTRUCTION FOR VALIDITY TESTING

Final Rejection §103
Filed
Mar 27, 2024
Examiner
CHOWDHURY, ZIAUL A.
Art Unit
2192
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
479 granted / 550 resolved
+32.1% vs TC avg
Strong +37% interview lift
Without
With
+36.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
11 currently pending
Career history
571
Total Applications
across all art units

Statute-Specific Performance

§101
16.6%
-23.4% vs TC avg
§103
52.3%
+12.3% vs TC avg
§102
20.3%
-19.7% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 550 resolved cases

Office Action

§103
Detailed Action The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is the initial office action based on the application filed on March 27th, 2024, which claim 1-25 have been presented for examination. Status of Claims Claims 1-25 are pending in the application, of which claims 1, 14, 19 and 24-25 are in independent form and these claims (1-25) are subject to following rejection(s) and/or objection(s) set forth in the following Office Action below. Claim Rejections – 35 USC §103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lichtenau et al. (US Patent Application Publication No. 2020/0264890 A1 -herein after Lichtenau) in view of Schwarz et al. (US PAT. No. 11,442,726 B1 herein after Schwarz). Per claim 1: Lichtenau discloses: A computer program product for facilitating processing within a computing environment, the computer program product (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method) comprising: a set of one or more computer readable storage media (At least see ¶[0011] - a computer readable storage medium); and program instructions, collectively stored in the set of one or more computer readable storage media (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method), for causing at least one computing device to perform the following computer operations including: executing an instruction to perform validity testing of a source value (At least see ¶[0011] -digit validation check control is enabled for execution of the instruction), the executing the instruction including: obtaining the source value using at least one field of the instruction (At least see ¶[0011] -obtaining an instruction to perform one or more operations using at least one input value); performing validity testing of at least a portion of the source value based on one or more test controls obtained using a field of the instruction (At least see ¶[0013] -performing a digit validation check on the at least one input value; also see ¶[0059] -field(s) or register(s) of the instruction); and providing the result for use in further processing (At least see ¶[0013] - output a result indicating, based on the validation, whether a digit check error exists with respect to the at least one input value). Lichtenau sufficiently discloses the program product as set forth above, but Lichtenau does not explicitly disclose: wherein the performing the validity testing determines whether a format of the at least the portion of the source value adheres to a data format variation specified by, at least, the one or more test controls, and wherein the performing the validity testing provides a result. However, Schwarz disclose: wherein the performing the validity testing determines whether a format of the at least the portion of the source value adheres to a data format variation specified by, at least, the one or more test controls, and wherein the performing the validity testing provides a result (At least see Col. 9:45-48 - result is not equal to zero and the sign is negative, and all digits and sign are valid, and no overflow. 2 The result is not equal to zero and the sign is positive, and all digits and sign are valid, and no overflow; also see FIG 4[Wingdings font/0xE0]416-418; where in “concatenated value, which is in one format, such as the zoned decimal format, is converted to another format, such as a signed packed decimal format, to provide a converted result; see Col. 11:30-33”). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 2: Schwarz also disclose: wherein the providing the result includes including the result in a condition code returned at completion of executing the instruction (At least see Col. 9:40-43 - When the Condition Code Set control is one, the condition code is set, as follows: 0 The result is equal to zero and all digits and sign are valid, and no overflow). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 3: Schwarz also disclose: wherein the source value is a decimal value in a zoned format and the data format variation is a zoned format variation (At least see Col. 11:38-43 - a signed packed decimal format operand in a vector register into a zoned decimal format operand in two vector registers with the high data unsigned and the low data signed. Either or both instructions can check the validity of the digits and sign code of the signed packed decimal format source). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 4: Schwarz also disclose: a separate sign control specifying whether the source value is to include a sign in a data unit of the plurality of data units separate from other data units of the plurality of data units that include digits (At least see Col. 2:54-57 -converting the at least a portion of the value includes converting selected digits of the value to obtain the converted result. The selected digits include, for instance, a leftmost fifteen digits of the value); and a leading sign specifying a particular data unit of the plurality of data units of the source value to include a sign of the source value (At least see Col. 11:30-34 - concatenated value, which is in one format, such as the zoned decimal format, is converted to another format, such as a signed packed decimal format, to provide a converted result 416. In one example, the signed packed decimal format includes 31 digits and a sign), and wherein the performing the validity testing includes: using the separate sign control and the leading sign to determine the data format variation for which the format of the at least the portion of the source value is to adhere (At least see Col. 11:43-46 -leftmost digit of the concatenated zoned decimal number is not placed in the signed packed decimal format, since the signed packed decimal format includes 31 digits and a sign); and checking that the format of the at least the portion of the source value complies to the data format variation (At least see Col. 9:24-27 -source vector digits are checked for validity for general operand data exceptions; if the No Sign Validation control is zero, then the source vector sign code is also checked for validity). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 5: Schwarz also disclose: based on selected settings of the separate sign control and the leading sign, the data format variation is an embedded leading sign type zoned format (At least see Col. 1:28-33 -signed zoned decimal format (also referred to as an embedded signed zoned decimal format) is similar to the unsigned zoned decimal format except that the zone field of the rightmost byte contains a 4-bit sign. There is also a separate signed zoned decimal format). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 6: Schwarz also disclose: based on particular settings of the separate sign control and the leading sign, the data format variation is a separate trailing sign type zoned format (At least see Col. 28:4-8 - formats used to represent numbers may be employed. As an example, aspects of the invention can be used for the numeric portion of separate signed zoned decimal formats, unsigned packed decimal formats, and/or other formats. Many variations are possible). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 7: Schwarz also disclose: based on chosen settings of the separate sign control and the leading sign, the data format variation is a separate leading sign type zoned format (At least see Col. 11:30-34 - concatenated value, which is in one format, such as the zoned decimal format, is converted to another format, such as a signed packed decimal format, to provide a converted result 416. In one example, the signed packed decimal format includes 31 digits and a sign). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 8: Schwarz also disclose: one or more test controls further include a disallowed spaces count specifying a number of selected data units of the plurality of data units of the source value not to contain characters representing spaces, and wherein the performing the validity testing includes using the separate sign control, the leading sign and the disallowed spaces count to determine the data format variation for which the format of the at least the portion of the source value is to adhere (At least see Col. 1:38-48 -Separate signed zoned decimal data items can range from 2 to 32 bytes to encode 1 to 31 decimal digits and a one byte sign code. Due to the large and variable size of zoned decimal data, it is currently supported only as a storage operand. Before operating on the zoned decimal data, for example to perform computations, it is converted to another format, such as packed decimal or decimal floating point. The results of the computations are then converted back to a zoned decimal storage operand. These conversions to and from memory are time-consuming, impacting performance of the computing environment). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 9: Schwarz also disclose: one or more test controls further include a digits count specifying a number of data units of the plurality of data units of the source value to contain a digit, and wherein the performing the validity testing includes using the separate sign control, the leading sign, the disallowed spaces count and the digits count to determine the data format variation for which the format of the at least the portion of the source value is to adhere (At least see Col. 1:38-48 -Separate signed zoned decimal data items can range from 2 to 32 bytes to encode 1 to 31 decimal digits and a one byte sign code. Due to the large and variable size of zoned decimal data, it is currently supported only as a storage operand. Before operating on the zoned decimal data, for example to perform computations, it is converted to another format, such as packed decimal or decimal floating point. The results of the computations are then converted back to a zoned decimal storage operand. These conversions to and from memory are time-consuming, impacting performance of the computing environment). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 10: Schwarz also disclose: based on defined settings of the separate sign control and the leading sign and based on the disallowed spaces count having a predetermined relationship with the digits count, the data format variation is an embedded trailing sign type zoned format (At least see Col. 1:36-42 - Embedded signed zoned decimal data items in, e.g., COBOL can range from 1 to 31 bytes to encode 1 to 31 decimal digits. Separate signed zoned decimal data items can range from 2 to 32 bytes to encode 1 to 31 decimal digits and a one byte sign code. Due to the large and variable size of zoned decimal data, it is currently supported only as a storage operand). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 11: Schwarz also disclose: based on defined settings of the separate sign control and the leading sign and based on the disallowed spaces count having a predefined relationship with the digits count, the data format variation is a spaced embedded trailing sign type zoned format (At least see Col. 1:36-42 - Embedded signed zoned decimal data items in, e.g., COBOL can range from 1 to 31 bytes to encode 1 to 31 decimal digits. Separate signed zoned decimal data items can range from 2 to 32 bytes to encode 1 to 31 decimal digits and a one byte sign code. Due to the large and variable size of zoned decimal data, it is currently supported only as a storage operand). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 12: Schwarz also disclose: wherein the source value includes a plurality of data units, and wherein the data format variation specifies one or more data unit formats for at least a set of data units of the plurality of data units, the one or more data unit formats being of a plurality of data unit formats (At least see Col. 2:13-27 - converting between a zoned decimal format and another format, operations on or using the data, e.g., by SIMD (single instruction, multiple data) instructions, are performed directly using the registers. For instance, the input and output are provided in the registers. This is more efficient than using memory to obtain the input and/or store the output. The operations are performed faster, reducing execution time, and improving processor and/or overall system performance. Further, by using registers for zoned decimal format, some operations, such as numeric editing and/or string processing of zoned decimal data items through the use of, e.g., a COBOL INSPECT statement, can be performed more efficiently by operating on the data in registers directly in the zoned decimal format). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 13: Schwarz also disclose: plurality of data units is a plurality of bytes, and wherein the plurality of data unit formats includes a sign and digit byte format, a zone and digit byte format, a space byte format, and a separate sign byte format (At :least see Col. 6:61-67 through Col. . - - a zoned decimal number includes 32 digits (e.g., 256 bits), and each digit is stored in a byte. For instance, a byte 200 of a zoned decimal number includes a zone portion (e.g., leftmost 4 bits) 202 and a digit portion (e.g., rightmost 4 bits) 204. Digit portion 204 includes a code representing a decimal digit. Decimal digits in the zoned format may be part of a larger character set, which includes alphabetic and special characters. The zone portion of the low order byte 206 (e.g., rightmost byte of a decimal operand) may include a sign 208 of the decimal number). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 14: Lichtenau discloses: A computer system for facilitating processing within a computing environment ¶[0012] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein, the computer system comprising: at least one computing device (At least see FIG 1A with associated text); a set of one or more computer readable storage media (At least see ¶[0011] - a computer readable storage medium); and program instructions, collectively stored in the set of one or more computer readable storage media (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method), for causing the at least one computing device to perform the following computer operations including: remaining limitation in the claim are as similar as claim 1 above; and therefore, rejected with the same rational. Per claim 15: Limitation rendered in this claim is as similar art claim 3 above; and therefore, rejected with the same rational. Per claim 16: Limitation rendered in this claim is as similar art claim 4 above; and therefore, rejected with the same rational. Per claim 17: Limitation rendered in this claim is as similar art claim 8 above; and therefore, rejected with the same rational. Per claim 18: Limitation rendered in this claim is as similar art claim 9 above; and therefore, rejected with the same rational. Per claim 19: Lichtenau discloses: A computer-implemented method of facilitating processing within a computing environment (At least see ¶[0011] - instructions for performing a method), the computer-implemented method comprising: remaining limitation in the claim are as similar as claim 1 above; and therefore, rejected with the same rational. Per claim 20: Limitation rendered in this claim is as similar art claim 3 above; and therefore, rejected with the same rational. Per claim 21: Limitation rendered in this claim is as similar art claim 4 above; and therefore, rejected with the same rational. Per claim 22: Limitation rendered in this claim is as similar art claim 8 above; and therefore, rejected with the same rational. Per claim 23: Limitation rendered in this claim is as similar art claim 9 above; and therefore, rejected with the same rational. Per claim 24: Lichtenau discloses: A computer program product for facilitating processing within a computing environment, the computer program product (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method) comprising: a set of one or more computer readable storage media (At least see ¶[0011] - a computer readable storage medium); and program instructions, collectively stored in the set of one or more computer readable storage media (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method), for causing at least one computing device to perform the following computer operations including: executing an instruction to perform validity testing of a source value (At least see ¶[0011] -digit validation check control is enabled for execution of the instruction), the executing the instruction including: performing validity testing of at least a portion of the source value based on a plurality of test controls obtained using a field of the instruction (At least see ¶[0013] -performing a digit validation check on the at least one input value; also see ¶[0059] -field(s) or register(s) of the instruction), the performing the validity testing comprising: providing the result for use in further processing (At least see ¶[0013] - output a result indicating, based on the validation, whether a digit check error exists with respect to the at least one input value). providing the result for use in further processing (At least see ¶[0013] - output a result indicating, based on the validation, whether a digit check error exists with respect to the at least one input value). Lichtenau sufficiently discloses the program product as set forth above, but Lichtenau does not explicitly disclose: determining that a format of the at least the portion of the source value adheres to a data format variation specified by, at least, one or more test controls of the plurality of test controls; and ascertaining, using at least one test control of the plurality of test controls, that one or more digits and a sign code of the at least the portion of the source value are valid. However, Schwarz disclose: determining that a format of the at least the portion of the source value adheres to a data format variation specified by, at least, one or more test controls of the plurality of test controls (At least see Col. 11:30-33 - concatenated value, which is in one format, such as the zoned decimal format, is converted to another format, such as a signed packed decimal format, to provide a converted result); and ascertaining, using at least one test control of the plurality of test controls, that one or more digits and a sign code of the at least the portion of the source value are valid (At least see Col. 9:45-48 - result is not equal to zero and the sign is negative, and all digits and sign are valid, and no overflow. 2 The result is not equal to zero and the sign is positive, and all digits and sign are valid, and no overflow; also see FIG 4[Wingdings font/0xE0]416-418). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). Per claim 25: Schwarz disclose: A computer program product for facilitating processing within a computing environment, the computer program product comprising: a set of one or more computer readable storage media (At least see ¶[0011] - a computer readable storage medium); and program instructions, collectively stored in the set of one or more computer readable storage media (At least see ¶[0011] - computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method), for causing at least one computing device to perform the following computer operations including: performing validity testing of the decimal number based on a plurality of test controls obtained using a field of the instruction (At least see ¶[0013] -performing a digit validation check on the at least one input value; also see ¶[0059] -field(s) or register(s) of the instruction), the performing the validity testing comprising: providing a result of the validity testing in a condition code of the instruction for use in further processing (At least see ¶[0013] - output a result indicating, based on the validation, whether a digit check error exists with respect to the at least one input value). Lichtenau sufficiently discloses the program product as set forth above, but Lichtenau does not explicitly disclose: executing an instruction to perform validity testing of a decimal number in a zoned format, the executing the instruction including: determining that a format of the decimal number adheres to a zoned format variation specified by, at least, one or more test controls of the plurality of test controls; and ascertaining, using at least one test control of the plurality of test controls, that one or more digits and a sign code of the decimal number are valid. However, Schwarz disclose: executing an instruction to perform validity testing of a decimal number in a zoned format (At least see Col. 437-40 - perform the pack operation, various operations are employed, such as, for instance, concatenating, converting, writing to a register, validity checking and/or condition code setting), the executing the instruction including: determining that a format of the decimal number adheres to a zoned format variation specified by, at least, one or more test controls of the plurality of test controls (At least see Col. 11:30-33 - concatenated value, which is in one format, such as the zoned decimal format, is converted to another format, such as a signed packed decimal format, to provide a converted result); and ascertaining, using at least one test control of the plurality of test controls, that one or more digits and a sign code of the decimal number are valid (At least see Col. 9:45-48 - result is not equal to zero and the sign is negative, and all digits and sign are valid, and no overflow. 2 The result is not equal to zero and the sign is positive, and all digits and sign are valid, and no overflow; also see FIG 4[Wingdings font/0xE0]416-418). It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate Schwarz into Lichtenau because use of registers, such as hardware vector registers, in converting between a zoned decimal format and another format, operations on or using the data; such as, single instruction, multiple data instructions, are performed directly using the registers, e.g. the input and output are provided in the registers, which is more efficient than using memory to obtain the input and/or store the output, and the operations are performed faster, reducing execution time, and improving processor and/or overall system performance (please see Col. 1:60-67 through Col. 2:1-27). CONCLUSION Prior arts made of record and have yet relied upon is considered pertinent to applicant's disclosure. See MPEP § 707.05 Carlough et al. (US 20130173892 A1) discloses “a format 400 of the Convert from Zoned instruction includes, for instance, the following fields: Opcode fields 402a, 402b: The opcode fields provide an opcode that indicates the function being performed by the instruction. As examples, one defined opcode defines the function as the long Convert from Zoned instruction, and another predefined opcode indicates it is an extended Convert from Zoned instruction. Length field (L.sub.2) 404: Length field 404 specifies the length (e.g., in bytes) of the second operand. As examples, the length field includes a length code of 0 to 33 for an extended Convert to Zoned instruction, and a length code of 0 to 15 for a long Convert from Zoned instruction.” (please refer to ¶[0070] through ¶[0073]). 7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZIAUL A. CHOWDHURY whose telephone number is (571)270-7750. The examiner can normally be reached on 9:30PM 6:30PM Monday -Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S. Sough can be reached on 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Status information for published applications may be obtained from Patent Public Search tool (for all users) – A link to the Patent Public Search Tool is available at www. Uspto.gov/PatentPublicSearch. To find a U.S. patent or U.S. patent application publication, open the Patent Public Search tool by selecting “Start search”. Type the U.S. patent or U.S. patent application publication number in the “Search” panel without any punctuation and followed by an”.pn.”. Should you have questions on access to the system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZIAUL A CHOWDHURY/ Primary Examiner, Art Unit 2192
Read full office action

Prosecution Timeline

Mar 27, 2024
Application Filed
Apr 14, 2026
Non-Final Rejection mailed — §103
Jun 08, 2026
Examiner Interview Summary
Jun 08, 2026
Applicant Interview (Telephonic)
Jun 17, 2026
Response Filed
Aug 14, 2026
Final Rejection mailed — §103 (current)

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SOFTWARE TEST SYSTEM AND SOFTWARE TEST METHOD
2y 12m to grant Granted Jul 07, 2026
Patent 12675265
DYNAMIC PATHWAYS FOR ARTIFICIAL INTELLIGENCE AND TENSOR COMPUTATION GRAPHS
2y 9m to grant Granted Jul 07, 2026
Patent 12650817
RELATIONSHIP-BASED DATA STRUCTURE GENERATION FOR ENHANCED VISUALIZATION OF INFORMATION RELATED TO SOFTWARE PRODUCTS OBTAINED FROM MULTIPLE DATA SOURCES
2y 8m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+36.8%)
3y 1m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 550 resolved cases by this examiner. Grant probability derived from career allowance rate.

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