DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/14/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US Pub. 2017/0162591).
Regarding independent claim 1, Choi teaches a semiconductor device (Fig. 1B; para. 0020+), comprising:
a source structure (SS1/ILS/SS2) disposed over a base (substrate; para. 0047) (Fig. 1B);
an etch prevention layer (ESS) disposed over the source structure (Fig. 1B; para. 0022);
bit lines (para. 0006);
a stack structure (STA) located between the etch prevention layer and the bit lines and including conductive layers (CP) and insulating layers (ILD) that are alternately stacked on each other, wherein one of the insulating layers (lowest ILD) forms an outer surface of the stack structure and is in direct contact with the etch prevention layer (Fig. 1B; para. 0021);
a channel structure passing through the stack structure and the etch prevention layer, wherein the channel structure includes a channel layer (CH) and a memory layer (ML1) (Fig. 1B; para. 0036);
a slit (SI or SA) passing though the stack structure and the etch prevention layer (Fig. 1B; para. 0021, 0026); and
a spacer (SWI) surrounding a sidewall of the etch prevention layer (Fig. 1B; para. 0021),
wherein a lower portion of the channel layer is located in the source structure and a sidewall of the lower portion of the channel layer is in direct contact with the source structure (Fig. 1B), and
wherein a thickness of the etch prevention layer is less than a thickness of at least one of the insulating layers (Fig. 1B – the thickness of the etch prevention layer is less than a thickness of the lowest ILD).
Re claim 3, Choi teaches wherein the source structure comprises: a first source layer (SS1) disposed over the base; and a second source layer (ILS/SS2) located between the first source layer and the etch prevention layer and in direct contact with the lower portion of the channel layer (Fig. 1B).
Re claim 4, Choi teaches wherein the etch prevention layer is interposed in an interface between the second source layer and the stack structure (Fig. 1B).
Re claim 5, Choi teaches wherein the channel structure further includes a gap-fill layer (CO), wherein the channel layer is disposed over a sidewall of the gap-fill layer, wherein the memory layer is disposed over a sidewall of the channel layer, and wherein the gap-fill layer passes through the stack structure, the etch prevention layer, and the second source layer (Fig. 1B; para. 0060).
Re claim 6, Choi teaches wherein a part of the lower portion of the channel layer is exposed, and an exposed part of the channel layer is in direct contact with the second source layer (Fig. 1B).
Re claim 7, Choi teaches wherein the lower portion of the channel layer extends into the first source layer and the first source layer is in contact with the memory layer (Fig. 1B).
Re claim 9, Choi teaches wherein the spacer is in contact of the stack structure (Fig. 1B).
Re claim 10, Choi teaches wherein the slit is filled with an insulating pattern (SI) (para. 0032).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Pub. 2017/0162591) in view of Lee et al. (US Pub. 2012/0119283).
Re claim 2, Choi teaches wherein the etch prevention layer may include carbon doped polysilicon (para. 0090), but is silent with respect to other possible materials.
Lee teaches the use of silicon carbonitride (SiCN) as a material for an etch stop layer (Fig. SE; para. 0126).
It would have been obvious to one of ordinary skill in the art at the time of filing to use silicon carbonitride (SiCN) as the etch stop material within the device of Choi for the purpose of providing the desired etch selectivity. Furthermore, it considered obvious to select a known material based on its suitability for an intended purpose (MPEP 2144.07).
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Pub. 2017/0162591) in view of AAPA*.
Re claim 8, Choi teaches wherein the source structure includes a silicon layer including one of an N-type and P-type dopant (para. 0052).
While Choi discloses the material to be a broader silicon, AAPA teaches that one of ordinary skill in the art at the time of filing would recognize that within the given context, the disclosed “silicon” would encompass the claimed polysilicon and one of ordinary skill in the art at the time of filing would further recognize the benefits of polysilicon over pure silicon such as; for example, simpler deposition.
*please note, that if applicant does not traverse the examiner’s assertion of Official Notice the common knowledge or well-known in the art statement is taken to be admitted prior art (MPEP 2144.03, C)
Claim(s) 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US Pub. 2017/0162591) in view of Yang et al. (US Pub. 2019/0287984).
Re claim 11, Choi teaches wherein the slit is filled with an insulating pattern.
Yang teaches a similar device (Fig. 2) wherein the slit (WLC) is filled with an insulating pattern or a conductive pattern for the purpose of forming a common source line (para. 0063), wherein the conductive pattern includes a polysilicon layer or metal (para. 0063).
It would have been obvious to one of ordinary skill in the art at the time of filing to fill the slit with a conductive pattern instead of an insulating pattern as taught by Yang to arrive at the claimed invention for the same purpose of forming a common source line.
Re claim 12, Choi teaches wherein the slit is filled with an insulating pattern.
Yang teaches a similar device (Fig. 2) wherein the slit (WLC) is filled with an insulating pattern or a conductive pattern for the purpose of forming a common source line (para. 0063), wherein the conductive pattern includes a single layer or a multilayer film (para. 0063).
It would have been obvious to one of ordinary skill in the art at the time of filing to fill the slit with a conductive pattern instead of an insulating pattern as taught by Yang to arrive at the claimed invention for the same purpose of forming a common source line.
Regarding independent claim 13, Choi teaches a semiconductor device (Fig. 1B; para. 0020+), comprising:
a source structure (SS1/ILS/SS2) disposed over a base (substrate; para. 0047) (Fig. 1B);
an etch prevention layer (ESS) disposed over the source structure (Fig. 1B; para. 0022);
bit lines (para. 0006);
a stack structure (STA) located between the etch prevention layer and the bit lines and including conductive layers (CP) and insulating layers (ILD) that are alternately stacked on each other (Fig. 1B; para. 0021);
a channel structure passing through the stack structure and the etch prevention layer (Fig. 1B; para. 0036);
a slit (SI or SA) passing though the stack structure and the etch prevention layer (Fig. 1B; para. 0021, 0026);
a spacer (SWI) disposed on a sidewall of the slit (Fig. 1B; para. 0021); and
wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure (Fig. 1B),
wherein the spacer covers an entire sidewall of the etch prevention layer (Fig. 1B), and
wherein a thickness of the etch prevention layer is less than a thickness of at least one of the insulating layers (Fig. 1B – the thickness of the etch prevention layer is less than a thickness of the lowest ILD).
Choi teaches wherein an insulating pattern is disposed in the slit (para. 0032).
Yang teaches a similar device (Fig. 2) wherein an insulating pattern or conductive pattern is disposed in the slit (WLC) for the purpose of forming a common source line (para. 0063).
It would have been obvious to one of ordinary skill in the art at the time of filing to fill the slit with a conductive pattern instead of an insulating pattern as taught by Yang to arrive at the claimed invention for the same purpose of forming a common source line.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/MOLLY K REIDA/ Examiner, Art Unit 2899