Prosecution Insights
Last updated: October 02, 2026
Application No. 18/618,800

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Mar 27, 2024
Priority
Jun 27, 2023 — RE 10-2023-0082442
Examiner
QURESHI, MARIAM
Art Unit
Tech Center
Assignee
Samsung Display Co., Ltd.
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
506 granted / 670 resolved
+15.5% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
46 currently pending
Career history
699
Total Applications
across all art units

Statute-Specific Performance

§103
58.8%
+18.8% vs TC avg
§102
26.2%
-13.8% vs TC avg
§112
12.7%
-27.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 670 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-17, 19-21, 23-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fujita (US Publication No.: US 2019/0206322 A1). Regarding Claim 1, Fujita discloses a display device (Figures 1-2) comprising: A first data line (Figure 1, data line 114); A first pixel connected to the first data line (Figure 1, first pixel 110), and comprising A driving transistor (Figure 2, driving transistor 140); and A first capacitor between a gate electrode of the driving transistor and the first data line (Figure 2, first capacitor 135; Paragraph 0046; Paragraph 0061). Regarding Claim 2, Fujita discloses the display device of claim 1, wherein the first capacitor overlaps the first data line and the gate electrode (Figure 2; Paragraph 0061). Regarding Claim 3, Fujita discloses the display device of claim 1, further comprising: a second data line adjacent to the first data line (Figure 1, second data line 114); and a second pixel connected to the second data line (Figure 1, second pixel 110). Regarding Claim 4, Fujita discloses the display device of claim 3, wherein the first capacitor is between the first data line and the gate electrode, and between the second data line and the gate electrode (Figure 2 discloses a first capacitor 135 located between the first data line and the gate electrode and the second data line and the gate electrode). Regarding Claim 5, Fujita discloses the display device of claim 3, wherein the second data line is more distant from the gate electrode than the first data line (Figures 1-2 disclose that the second data line is more distant from the gate electrode 140c than the first data line). Regarding Claim 6, Fujita discloses the display device of claim 3, wherein the first pixel and the second pixel are between the first data line and the second data line (Figure 2, as annotated below). PNG media_image1.png 556 488 media_image1.png Greyscale Regarding Claim 7, Fujita discloses the display device of claim 3, wherein the first pixel and the second pixel are configured to provide light of a same color (Figure 2 discloses that all pixel circuits 110 are identical and would therefore provide light of same colors). Regarding Claim 8, Fujita discloses the display device of claim 1, wherein the first capacitor comprises: a first capacitor electrode comprising electrodes spaced apart from each other to have a gap (Figure 5, electrodes 43 and 42; Paragraph 0090); An insulating layer above the first capacitor electrode (Figure 5, insulating layer 11); and A second capacitor electrode above the insulating layer, and overlapping the gap and the electrodes of the first capacitor electrode (Figure 5, second capacitor electrode 21). Regarding Claim 9, Fujita discloses the display device of claim 8, wherein at least part of the second capacitor electrode is between adjacent electrodes (Figure 5, second capacitor electrode 21 is between first capacitor electrodes 42 and 43). Regarding Claim 10, Fujita discloses the display device of claim 8, wherein the second capacitor electrodes overlaps an entirety of the first capacitor electrode (Paragraph 0134). Regarding Claim 11, Fujita discloses the display device of claim 8, wherein an end of the second capacitor electrode extends further in one direction than an end of the first capacitor electrode (Figure 5, the left end of the second capacitor electrode 21 extends further than that of the first capacitor electrode 43). Regarding Claim 12, Fujita discloses the display device of claim 1, wherein the first capacitor comprises: a first insulating layer comprising layers having stepped portions of different respective sizes (Figure 5, discloses a first insulating layer having stepped portions); a first capacitor electrode above the first insulating layer, and having stepped portions corresponding to the stepped portions of the first insulating layer (Figure 5, first capacitor electrode 43 has a stepped portion at least at 34); a second insulating layer above the first capacitor electrode, and having stepped portions corresponding to the stepped portions of the first capacitor electrode (Figure 5, second insulating layer 10 has corresponding stepped portions at least at 34); and a second capacitor electrode above the second insulating layer (Figure 5, second capacitor electrode 21 has a stepped portion at least at 33). Regarding Claim 13, Fujita discloses the display device of claim 12, wherein the first capacitor electrode has a large number of layers than the first insulating layer (Figure 5, first capacitor electrode has multiple layers 43/52/72). Regarding Claim 14, Fujita discloses the display device of claim 8, wherein the first capacitor electrode comprises: a first electrode extending in a first direction (Figure 5, first electrode 43); and second electrodes extending from the first electrode in a second direction crossing the first direction, adjacent ones of the second electrodes being spaced a part such that a gap exists therebetween (Figure 5, second electrodes 52/72, where a gap exists therebetween). Regarding Claim 15, Fujita discloses the display device of claim 8, wherein the first capacitor electrode comprises: a first electrode having closed curve shape (Figure 5, first electrode 43 has a curve shape at least at 34); and second electrode inside the first electrode in plan view, and extending in one direction from the first electrode, adjacent ones of the second electrodes being spaced apart such that a gap exists therebetween (Figure 5, second electrodes 52/72). Regarding Claim 16, Fujita discloses the display device of claim 8, wherein the first capacitor electrode comprises: a first electrode having a closed curve shape; and second electrodes inside the first electrode in plan view, and respectively extending from the first electrode in a first direction and a second direction, wherein the second electrodes in the first direction and the second electrodes in the second direction substantially perpendicularly intersect each other, and wherein adjacent ones of the second electrodes are spaced apart such that a gap exists therebetween (Figure 5, first electrode 43 has a curve shape at least at 34, second electrodes 52/72). Regarding Claim 17, Fujita discloses the display device of claim 8, wherein the first capacitor electrode comprises: a first electrode having a closed curve shape; and second electrodes inside the first electrode in plan view, and respectively extending in a first oblique direction and in a second oblique direction from the first electrode, wherein the second electrodes in the first oblique direction and the second electrodes in the second oblique direction substantially perpendicularly intersect each other, and wherein adjacent ones of the second electrodes are spaced apart such that a gap exists therebetween (Figure 5, first electrode 43 has a curve shape at least at 34, second electrodes 52/72). Regarding Claim 19, Fujita discloses the display device of claim 1, further comprising a second capacitor above the first capacitor (Figure 2 discloses multiple capacitors 135). Regarding Claim 20, Fujita discloses the display device of claim 19, wherein the second capacitor is at a same layer as the first data line (Figure 5, capacitor 135 is at a same layer as first data line 114). Regarding Claim 21, Fujita discloses the display device of claim 19, wherein the second capacitor comprises: a first capacitor electrode; and a second capacitor electrode adjacent to the first capacitor electrode, and at a same layer as the first capacitor electrode (Figure 5, first capacitor electrode 43, second capacitor electrode 42). Regarding Claim 23, Fujita discloses the display device of claim 8, further comprising: a first connection electrode connected to the first capacitor electrode; a second connection electrode above the first connection electrode; and a third connection electrode connecting the first connection electrode to the second connection electrode, and between the first connection electrode and the second connection electrode (Figure 5, connection electrodes 52/72/92). Regarding Claim 24, Fujita discloses a display device (Figures 1-5) comprising: a substrate (Figure 5, substrate 2); a transistor above the substrate (Figure 5, transistor 140/130); a first data line above the transistor (Figures 1-5, first data line 114); and a capacitor between a gate electrode of the transistor and the first data line (Figures 1-5, capacitor 135). Regarding Claim 25, Fujita discloses the display device of claim 24, wherein the first capacitor overlaps the first data line and the gate electrode (Figure 2; Paragraph 0061). Regarding Claim 26, Fujita discloses the display device of claim 26, further comprising: a second data line adjacent to the first data line (Figure 1, second data line 114); and a second pixel connected to the second data line (Figure 1, second pixel 110). Regarding Claim 27, Fujita discloses the display device of claim 26, wherein the capacitor is between the first data line and the gate electrode, and between the second data line and the gate electrode (Figure 2 discloses a first capacitor 135 located between the first data line and the gate electrode and the second data line and the gate electrode). Regarding Claim 28, Fujita discloses the display device of claim 26, wherein the second data line is more distant from the gate electrode than the first data line (Figures 1-2 disclose that the second data line is more distant from the gate electrode 140c than the first data line). Regarding Claim 29, Fujita discloses the display device of claim 24, wherein the first capacitor comprises: a first capacitor electrode comprising electrodes spaced apart from each other to have a gap (Figure 5, electrodes 43 and 42; Paragraph 0090); An insulating layer above the first capacitor electrode (Figure 5, insulating layer 11); and A second capacitor electrode above the insulating layer, and overlapping the gap and the electrodes of the first capacitor electrode (Figure 5, second capacitor electrode 21). Regarding Claim 30, Fujita discloses the display device of claim 29, wherein at least part of the second capacitor electrode is between adjacent electrodes (Figure 5, second capacitor electrode 21 is between first capacitor electrodes 42 and 43). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al (US Publication No.: US 2024/0014201 A1, “Tanaka”). Regarding Claim 18, Fujita discloses the display device of claim 8. Fujita fails to disclose that the first capacitor electrode comprises first electrodes and second electrodes having a spiral structure extending outwardly while rotating in a counterclockwise direction from a central portion, wherein adjacent ones of the first electrodes are spaced apart such that a gap exists therebetween, and wherein adjacent ones of the second electrodes are spaced apart such that a gap exists therebetween. However, Tanaka discloses a similar device where the first capacitor electrode comprises first electrodes and second electrodes having a spiral structure extending outwardly while rotating in a counterclockwise direction from a central portion, wherein adjacent ones of the first electrodes are spaced apart such that a gap exists therebetween, and wherein adjacent ones of the second electrodes are spaced apart such that a gap exists therebetween (Tanaka, Figure 8, first electrodes 56A, second electrodes 56B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the electrodes as disclosed by Fujita to have a spiral shape as disclosed by Tanaka. One would have been motivated to do so for the purpose of optimizing wire spacing and capacitance (Tanaka, Paragraph 0144). Allowable Subject Matter Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: -Chen (US 2020/0227500 A1) discloses a display device comprising a capacitor (Chen, Figures 1-5). Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIAM QURESHI whose telephone number is (571)272-4434. The examiner can normally be reached 9AM-5PM EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Caley can be reached at 571-272-2286. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARIAM QURESHI/Examiner, Art Unit 2871
Read full office action

Prosecution Timeline

Mar 27, 2024
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
98%
With Interview (+22.3%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 670 resolved cases by this examiner. Grant probability derived from career allowance rate.

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