DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 07/10/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over WU (US 20210225865 A1), hereinafter “Wu,” in view of ZHANG et al. (US 20210057433 A1), hereinafter “Zhang.”
Re: Independent Claim 1, Wu discloses a method used in forming memory circuitry comprising strings of memory cells (See Fig. 13; ¶0026: fabrication process of a 3D memory device), comprising:
forming vertically-alternating tiers of different composition first and second materials (Fig. 1: alternating stack layers 141 and 142; Fig. 13, step 212), the second material being insulative (¶0029: layers 141 and 142 may include a dielectric layer and a conductive layer), the vertically-alternating tiers comprising a stack comprising laterally-spaced memory blocks (Fig. 4: 30 memory device 100, layer stack 140; ¶0034: 3D memory device 100 has NAND memory cells configured in the layer stack 140. The layer stack 140 may be divided into multiple memory blocks... a memory block region 101, corresponding to a memory block, may include a channel hole region 102 that may include a first gate line slit (GLS) region 160.... the memory block region 101 is configured between the pair of the GLS's 170 in the Y direction.);
forming an inter-block column ... (a) through the vertically-alternating tiers longitudinally-along and between immediately-laterally-adjacent of the memory blocks (Fig. 4: gate line slits (GLS) 170, i.e., inter-block column, extend through the stack longitudinally along and between adjacent memory blocks; Fig. 13, step 214; ¶0034: memory block region 101 is separated from other memory block regions (not shown) by a pair of GLS's 170 that represent second GLS regions. As shown in FIG. 4, the memory block region 101 is configured between the pair of the GLS's 170 in the Y direction; see ¶0036);
forming an intra-block column of openings through the vertically-alternating tiers longitudinally-along and within individual of the memory blocks (Fig. 4: gate line slit (GLS) region 160, i.e., intra-block column of openings; ¶0034: a memory block region 101, corresponding to a memory block, may include a channel hole region 102 that may include a first gate line slit (GLS) region 160; ¶0035: In some embodiments, the GLS's 161 may have the same shape as and similar dimensions to that of the channel hole 150.), individual of the intra-block columns of openings being entirely within one of the individual memory blocks (Fig. 4: GLS 160 is entirely within individual memory block region 101; ¶0035: the first GLS region 160 may extend along both the X and Y directions.);
flowing a first etchant into the inter-block columns ... (b) and into the intra-block columns of openings to etch the first material of the first-material tiers selectively relative to the second-material tiers to form a void-space tier vertically between immediately-vertically-adjacent of the second-material tiers (Fig. 13, step 217; ¶0037: As shown in FIG. 5, the GLS's 161 and 170 each extend through the layer stack 140 and reach or partially penetrate the polysilicon layer 130 in the Z direction. As such, at the bottom of the GLS's 161 and 170, parts of the polysilicon layer 130 are exposed, i.e., in other words, etchant is deposited into both inter-block columns and intra-block column openings... Because of the GLS's 161 ... becomes faster and easier to etch out the layer 130 to form a cavity, ... In addition, because of the GLS's 161, more parts or a larger total area of the stack layers 142 is exposed. Similarly, it becomes faster and easier to etch out the layers 142, i.e., first material etching, to form cavities, i.e., void-space tiers; see ¶0048; ¶0050: sacrificial layers 142 are etched and the conductor layers 143 are deposited... Because the GLS 161 is configured around the middle region between the GLS's 170, the length of the narrow and long spacing between the layers 141 is cut by half; see ¶0061);
filling the void-space tiers with conductive material by flowing the conductive material or one or more precursors thereof through the inter-block columns ... (b) and through the intra-block columns of openings into the void-space tiers (Fig. 13, step 218; ¶0050: sacrificial layers 142 are etched and the conductor layers 143 are deposited; ¶0061: layer stack includes two dielectric stack layers and one of the stack layers is sacrificial. The sacrificial stack layers may be etched away at 217 to leave cavities, which then may be filled with an electrically conductive material to form conductor layers at 218, i.e., in other words, conductive material is deposited into both inter-block columns and intra-block column openings; see ¶¶ 0037, 0048 and 0087); and
... (b).
However, Wu does not specifically disclose wherein the inter-block openings are a column of (a) ... of openings and
(b) flowing a second etchant into the inter-block columns of openings to remove the conductive material from being between the immediately-laterally-adjacent memory blocks in individual of the filled void-space tiers.
In a similar field of endeavor, Zhang discloses forming an inter-block column of openings through the vertically-alternating tiers longitudinally-along and between immediately-laterally-adjacent of the memory blocks (Fig. 1: memory-block regions 58 and holes 60; Fig. 6: holes 81; ¶0029: Alternately, and by way of example only, horizontally-elongated trenches may be formed in the respective upper or lower stacks instead of holes.; ¶0030: lower-elevationally-extending holes (e.g., 60) in the lower stack that are laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent lower-memory-block regions; see ¶¶0018, 0022 and 0033 and Figs. 6-7);
... of openings (Fig. 1: memory-block regions 58 and holes 60, i.e., inter-block column of openings)
flowing a second etchant into the inter-block columns of openings to remove the conductive material from being between the immediately-laterally-adjacent memory blocks in individual of the filled void-space tiers (Fig. 1: memory-block regions 58 and holes 60; Fig. 6: holes 81; ¶0023: Referring to FIG. 8, sacrificial material 59 (not shown) has been removed (e.g., by anisotropic and/or isotropic etching) from lower holes 60 through upper holes 81; ¶0024: Referring to FIGS. 9 and 10, and in one embodiment, material 26 (not shown) of conductive tiers 22 has been removed, for example by being isotropically etched away through upper holes 81 and lower holes 60; see ¶0025 and Figs. 11-15).
Wu already uses the block-edge opening as a replacement-gate port: etchant and conductor travel through GLS 170 and through interior GLS 161 so sacrificial layers are removed, and conductive material is deposited. Wu forms 170 as one continuous GLS.
Zhang uses the same inter-block location for the same chemistry, but as column of holes 60/80. Zhang expressly treats holes and trenches as alternatives for that location between blocks (¶0029: Alternately, and by way of example only, horizontally-elongated trenches may be formed in the respective upper or lower stacks instead of holes.). After fill, the holes are filled with insulation material leaving insulative pillars 61 between adjacent blocks. Those pillars keep insulative material extending across the space between blocks around holes 60/81 and laterally across space 75 (See ¶0022). Therefore, Zhang assigns holes 60/81 the same functions as Wu assigns 170, e.g., edge access for nitride-out and W-in. Zhang discloses holes as a known alternative to a continuous trench. Swapping alternatives at the same place, for the same etch/fill, is predictable.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have substituted Wu’s gate line slits (170) with holes 60/80 because Zhang uses holes 60/81 at that same inter-block location for the same etch-and-fill and treats holes and trenches as alternatives. Substituting Zhang’s hole column for Wu’s continuous GLS 170 is a simple substitution of one known geometry for another to obtain the same, predictable replacement-gate access and inter-block isolation. See MPEP 2143(I)(B); KSR, 550 U.S. at 416, 82 USPQ2d at 1395; MPEP 2144.06.
Re: Claim 2, the combination of Wu and Zhang discloses the method of claim 1.
Wu further discloses comprising forming the inter-block columns of openings and the intra-block columns of openings simultaneously (Fig. 4: 161 and 170; Fig. 13, step 214: first and second GLS’s formed at the same time; ¶0037: The GLS's 161 and 170 may be formed by, e.g., a dry etch process or a combination of dry and wet etch processes. As shown in FIG. 5, the GLS's 161 and 170 each extend through the layer stack 140 and reach or partially penetrate the polysilicon layer 130 in the Z direction.).
Re: Claim 3, the combination of Wu and Zhang discloses the method of claim 1.
Zhang further discloses comprising forming the inter-block columns of openings and the intra-block columns of openings at different times (¶0018: Lower holes 60 when so-formed may be formed commensurately with formation of lower channel openings 25 if lower channel openings are so-formed. Alternately, such may be formed before or after forming lower channel openings 25 if lower channel openings are so-formed.; ¶0029: FIGS. 24-26 show another alternate embodiment construction 10 b wherein lower holes 60 are in lower stack 18 and upper-horizontally-elongated trenches 84 are in upper stack 35; In other words, Zhang teaches that openings may be formed before or after other openings ¶0018.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified Wu with steps disclosed by Zhang. There are only two options for the relative timing of two sets of openings: the same time or different times. Choosing between them is obvious to try, with predictable results (KSR, 550 U.S. at 421). Selecting a sequence for process steps is likewise prima facie obvious absent unexpected results (In re Burhans, 154 F.2d 690 (CCPA 1946)). See MPEP 2144.04.
Re: Claim 4, the combination of Wu and Zhang discloses the method of claim 1.
Wu further discloses comprising forming the intra-block columns of openings to be laterally-centered within the individual memory blocks (Fig. 4: holes 161 are centered.; ¶0035: The first GLS region 160 may include a certain number of GLS's 161 and in some embodiments may extend along the X direction. In some other embodiments, the first GLS region 160 may extend along both the X and Y directions.; See ¶0093).
Re: Claim 5, the combination of Wu and Zhang discloses the method of claim 1.
Wu further discloses comprising:
forming multiple of the intra-block column of openings through the vertically-alternating tiers longitudinally-along and within the individual memory blocks (Fig. 16 shows multiple GLS 164 having holes 165);
flowing the first etchant into the multiple intra-block columns of openings within the individual memory blocks to etch the first material of the first-material tiers selectively relative to the second-material tiers to form the void-space tier vertically between the immediately-vertically-adjacent second-material tiers (¶0071: channel hole region 106 may include the first GLS regions 164 that may include multiple GLS's 165 around the middle region between the GLS's 172; ¶0075: When more than one row of the GLS's 165 are formed between a pair of the GLS's 172, the process to etch a sacrificial layer, e.g., the layers 130 and 142 of the device 100, may become faster and more complete.; see ¶0080 and Fig. 17); and
filling the void-space tiers with the conductive material by flowing the conductive material or one or more precursors thereof through the multiple intra-block columns of openings within the individual memory blocks into the void-space tiers (¶0065: one or more deposition processes, one or more etch processes, and/or one or more filling processes used for the device 100 may be used in the fabrication of the device 300.).
Re: Claim 6, the combination of Wu and Zhang discloses the method of claim 5.
Wu further discloses wherein one of the multiple intra-block columns of openings within the individual memory blocks is laterally-centered therein (See ¶¶0071-0073: discloses multiple variations of GLS 164 configurations; ¶0073: GLS's 165 may be arranged around the middle region between the GLS's 172.; see ¶¶0044 and 0050).
Re: Claim 7, the combination of Wu and Zhang discloses the method of claim 5.
Wu further discloses wherein none of the multiple intra-block columns of openings within the individual memory blocks is laterally-centered therein (Fig. 16: multiple 164 not laterally-centered; see ¶¶0072, 80 and Figs. 16-17).
Re: Claim 9, the combination of Wu and Zhang discloses the method of claim 1.
Wu further discloses comprising forming channel-material strings of the strings of memory cells before forming the conductive material (Fig. 13, step 213; See ¶¶0030-0033: Wu forms the channel holes, functional layers and channel layers before the GLS’s, the sacrificial etch in step 217 and the conductor fill in step 218; Also see Zhang ¶0021, Figs. 4-5, and ¶0024: before conducting material 48).
Re: Claim 11, the combination of Wu and Zhang discloses the method of claim 1.
Zhang further discloses wherein, prior to removing the conductive material from being between the immediately-laterally-adjacent memory blocks in the individual filled void-space tiers:
the conductive material is formed in the inter-block columns of openings and in the intra-block columns of openings (¶0024: conducting material 48 is formed in the holes); and
etching the conductive material from the inter-block columns of openings and from the intra-block columns of openings and to form an annular void-space circumferentially around the inter-block columns of openings and the intra-block columns of openings in individual of the void-space tiers (See Figs. 11, 13-14, expanded regions 29; ¶0025: Such processing may comprise isotropic wet etching of conducting material 48 whereby interconnected holes 81/60 effectively radially expand in conductive tiers 22... Such may result in conducting material 48 being laterally-recessed relative to the initially-formed upper and lower holes 81/60; see ¶0028: pillars 61 comprise vertically-spaced and radially-projecting insulative rings 63 in conductive tiers 22 as compared to the insulative tiers 20; ¶0035: pillars comprise vertically-spaced and radially-projecting insulative rings (e.g., 63); In other words, the resulting radial gap is a void space circumferentially around each opening in each conductive tier. It is later filled with insulative rings 64; see Figs. 16-20).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified Wu in view of Zhang. Conductive material deposited through Wu’s GLS’s 161 would line those slits. If left, it would short vertically-adjacent conductor layers 143 and the later-formed ACS’s, which Wu isolates with insulating layer 192 (Wu ¶¶0051-0052). A person having ordinary skill in the art would remove it from both the intra-block and inter-block openings using Zhang’s etch, producing the annular recess around each (See Zhang, ¶¶0025, 0028 and 0035).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over WU (US 20210225865 A1) in view of ZHANG et al. (US 20210057433 A1) and GREENLEE et al. (US 10,361,216 B2, see IDS), hereinafter “Greenlee.”
Re: Claim 8, the combination of Wu and Zhang discloses the method of claim 1.
However, the combination of Wu in view of Zhang does not disclose wherein the intra-block columns of openings are completely masked while flowing the second etchant into the inter-block columns of openings to preclude the second etchant from flowing therein.
In a similar field of endeavor, Greenlee discloses wherein the intra-block columns of openings are completely masked while flowing the second etchant into the inter-block columns of openings to preclude the second etchant from flowing therein (col. 4, lns. 4-35: selectively masking a subset of vertically-extending openings while etching the solid material in the others. The channel openings are masked during the etch that recesses the dummy-structures and trench fill (Fig. 22 embodiment). Greenlee also describes “masking of the dummy structures” while material is removed from the channel openings in discussion of Fig. 4 alternatives.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have modified the process of Wu in view of Zhang with Greenlee. Once Wu’s intra-block openings are combined with Zhang’s isotropic inter-block etch, continuing that etch through the intra-block openings would laterally recess wordline material in the block interior. Wu stresses that gate electrodes across the intra-block openings must remain electrically connected (See Wu ¶¶ 0035, 0091, 0094). A person having ordinary skill in the art would therefore mask the intra-block openings, using Greenlee’s known selective-masking technique, so the second etchant acts only through the inter-block openings (col. 4, lns. 4-35).
Re: Claim 10, the combination of Wu and Zhang discloses the method of claim 1.
However, the combination of Wu in view of Zhang does not disclose comprising forming channel-material strings of the strings of memory cells after forming the conductive material.
In a similar field of endeavor, Greenlee discloses comprising forming channel-material strings of the strings of memory cells after forming the conductive material (See Figs. 6-9; col. 4, lns. 50-67: Referring to FIG. 6, void space 28 has been filled with conductive material 30 by flowing conductive material 30 (or one or more precursors thereof) through channel openings 26 to into void space 28... conductive material 30 may form a control gate of a charge-storage transistor and comprise part of an access line electrically coupling a row line or column line of such transistors.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have formed the memory-cell films and channel material after the etch and metal-precursor steps in order to keep those films from being exposed to materials during previous steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Machkaoutsan et al. (US 20210125919 A1) – Figs. 1-7 disclose features relevant to the current claims.
King (US 20220059566 A1) – See Figs. 2, 3 and 5-19; Pillars 60 adjacent memory-block regions; intervening openings 61 between those pillars; sacrificial material in the first tiers etched away and replaced with conducting material through the openings; intervening material formed in the openings after that etch [0020]-[0023]; Also see [0069], [0080]
Lee et al. (US 20160260735 A1) – See Figs. 1A, 1B, 3 and 5. First slit SI separates the stacks. Dummy holes DH sit between string pillars, shallower than the slit. Sacrificial layers are removed though the slit and the dummy holes; then conductive line patterns are formed. DH is filled with dummy insulating plug DI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898
