DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, claims 16-25 in the reply filed on July 28, 2026 is acknowledged.
Claims 1-15 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on July 28, 2026.
Claim Objections
Claim 25 is objected to because of the following informalities: “of” should be inserted after “an upper portion” (line 23). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16, 20 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/0285357 A1 (hereinafter “Yang”).
Regarding claim 16, Yang discloses in Figs. 1, 4, 38 and related text a microelectronic device (10; [0027]), comprising:
a semiconductor base structure (16; [0028]) comprising pillar structures (52; [0041]) horizontally separated from one another by filled isolation trenches (56, 58; [0042]);
word lines (28 (28a, 28b); [0031] and [0044]) horizontally extending through the pillar structures and the filled isolation trenches in a first direction (horizontal direction in the top view of Fig. 1);
a first dielectric stack (204, 220; [0097]) vertically overlying the pillar structures, the filled isolation trenches, and the word lines;
digit line contacts (70; [0049]) partially vertically extending through the first dielectric stack and into digit line contact regions (22; [0049]) of the pillar structures;
digit lines (26 (68); [0048]) over and in contact with the digit line contacts and partially vertically extending through the first dielectric stack, the digit lines horizontally extending in a second direction (vertical direction in the top view of Fig. 1) orthogonal to the first direction;
a second dielectric stack (214, 216; [0066] and [0077]) over the digit lines and the first dielectric stack;
storage node contacts (77 (76); [0052]) vertically extending partially through the second dielectric stack, completely through the first dielectric stack, and into storage node contact regions (18, 20; [0052]) of the pillar structures; and
redistribution layer (RDL) structures (32 (90, 92); [0026] and [0057]) over and in contact with the storage node contacts, the RDL structures partially vertically extending through the second dielectric stack.
Regarding claim 20, Yang discloses the digit lines and the digit line contacts each comprise substantially the same conductive material (e.g., Ti; [0048]-[0049]); and
the digit line contacts are unitary with the digit lines (if titanium (Ti) is selected as the material for both the digit line contacts and the digit lines in accordance with Yang’s disclosure in [0048]-[0049], then the resulting structure will be a unitary structure).
Regarding claim 22, Yang discloses the second dielectric stack comprises:
a first dielectric material (214; Fig. 38; [0066]) over the digit lines and the first dielectric stack; and
a second dielectric material (216; Fig. 38; [0077]) over the first dielectric material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang.
Regarding claim 17, Yang discloses the microelectronic device of claim 16.
Yang does not explicitly disclose lower surfaces of the digit line contacts and the storage node contacts individually vertically overlie upper surfaces of the word lines by at least 10 nanometers (nm).
Examiner submits that the vertical separation between lower surfaces of the digit line contacts and the storage node contacts and upper surfaces of the word lines is a result-effective variable. The “variable” is the vertical separation, and the “result” is parasitic capacitance. One of ordinary skill in the art understands that as the separation between conductive surfaces decreases, the parasitic capacitance increases in accordance with the well-known formula C=kA/d where C is the capacitance, k is the dielectric constant of the dielectric medium between the conductive surfaces, A is the overlapping area between the conductive surfaces on opposite sides of the dielectric medium, and d is the distance (separation) between the conductive surfaces on opposite sides of the dielectric medium. Conversely, as the separation between conductive surfaces increases, the parasitic capacitance decreases. Therefore, it is respectfully submitted that the vertical separation between lower surfaces of the digit line contacts and the storage node contacts and upper surfaces of the word lines is a result-effective variable that may be optimized by one of ordinary skill in the art.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to arrange lower surfaces of the digit line contacts and the storage node contacts to individually vertically overlie upper surfaces of the word lines by at least 10 nanometers (nm) in order to ensure that both a first parasitic capacitance between the digit lines and the word lines and a second parasitic capacitance between the redistribution layer (RDL) structures and the word lines do not exceed tolerable limits determined by the intended use of the microelectronic device.
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of US 2022/0336469 A1 (hereinafter “Breil”).
Regarding claim 18, Yang discloses the microelectronic device of claim 16.
Yang does not disclose each of the digit line contacts and each of the storage node contacts individually comprise: a lower region comprising epitaxial semiconductor material; an upper region comprising metal material; and a middle region vertically interposed between the lower region and the upper region and comprising metal silicide material.
Breil teaches in Fig. 1 and related text each of the digit line contacts and each of the storage node contacts (see Abstract) individually comprise:
a lower region (110; [0028]-[0029]) comprising epitaxial semiconductor material;
an upper region (114; [0032]) comprising metal material; and
a middle region (112; [0031]) vertically interposed between the lower region and the upper region and comprising metal silicide material.
Yang and Breil are analogous art because they both are directed to dynamic random access memory (DRAM) devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Breil because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form each of the digit line contacts and each of the storage node contacts to individually comprise: a lower region comprising epitaxial semiconductor material; an upper region comprising metal material; and a middle region vertically interposed between the lower region and the upper region and comprising metal silicide material, as taught by Breil, in order to form contact structures with reduced leakage current and resistance, as well as improved thermal stability, thereby creating a DRAM bit line (i.e., digit line) contact and a DRAM storage node contact with decreased contact resistance, thus facilitating improved DRAM systems (Breil: [0021]).
Regarding claim 19, Yang in view of Breil disclose the microelectronic device of claim 18.
Yang in view of Breil do not disclose the digit lines are integral and continuous with the digit line contacts; and the RDL structures are integral and continuous with the storage node contacts.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the digit lines to be integral and continuous with the digit line contacts and to form the RDL structures to be integral and continuous with the storage node contacts because it has been held that making integral requires only ordinary skill in the art and hence is considered a routine expedient. In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965). MPEP 2144.04(V)(B).
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of US 2024/0334684 A1 (hereinafter “Kim”).
Regarding claim 21, Yang discloses the microelectronic device of claim 16.
Yang does not disclose a maximum horizontal dimension of one of the digit line contacts in the first direction is less than or equal to a maximum horizontal dimension of one of the digit lines in the first direction.
Kim teaches in Fig. 4 and related text a maximum horizontal dimension (W1; [0040]) of one of the digit line contacts (DC; [0038]) in the first direction (D2; [0040]) is less than or equal to a maximum horizontal dimension (W4; [0040]) of one of the digit lines (BL; [0040]) in the first direction.
Yang and Kim are analogous art because they both are directed to dynamic random access memory (DRAM) devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Kim because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a maximum horizontal dimension of one of the digit line contacts in the first direction to be less than or equal to a maximum horizontal dimension of one of the digit lines in the first direction, as taught by Kim, in order to provide a semiconductor memory device with improved electrical and reliability characteristics (Kim: [0005] and [0041]).
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of US 2015/0076612 A1 (hereinafter “Maki”).
Regarding claim 23, Yang discloses the microelectronic device of claim 16.
Yang does not disclose the storage node contacts each have an elongate horizontal cross-sectional shape.
Maki teaches in Fig. 5 and related text the storage node contacts (SC; [0084]) each have an elongate horizontal cross-sectional shape.
Yang and Maki are analogous art because they both are directed to dynamic random access memory (DRAM) devices (Maki: [0098]) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Maki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form the storage node contacts to each have an elongate horizontal cross-sectional shape, as taught by Maki, because it has been held that change in shape, in the absence of persuasive evidence that the particular configuration is significant, is a matter of design choice involving only ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04(IV)(B).
Regarding claim 24, Yang discloses the microelectronic device of claim 16.
Yang does not disclose at least some of the storage node contacts individually have a parallelogram horizontal cross-sectional shape.
Maki teaches in Fig. 5 and related text at least some of the storage node contacts (SC; [0084]) individually have a parallelogram horizontal cross-sectional shape (note: a rectangle is simply a parallelogram having four 90° interior angles).
Yang and Maki are analogous art because they both are directed to dynamic random access memory (DRAM) devices (Maki: [0098]) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Yang with the specified features of Maki because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form at least some of the storage node contacts to individually have a parallelogram horizontal cross-sectional shape, as taught by Maki, because it has been held that change in shape, in the absence of persuasive evidence that the particular configuration is significant, is a matter of design choice involving only ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). MPEP 2144.04(IV)(B).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0303570 A1 (hereinafter “Lee”) in view of Yang.
Regarding claim 25, Lee discloses in Fig. 7 and related text an electronic system (700; [0037]), comprising:
an input device (702; [0037]);
an output device (704; [0037]);
a processor device (706; [0037]) operably coupled to the input device and the output device; and
a memory device (708; [0037]) operably coupled to the processor device.
Lee does not disclose the memory device comprising at least one microelectronic device structure comprising: a base structure comprising semiconductive pillar structures horizontally separated from one another by filled isolation trenches; word lines extending through the semiconductive pillar structures and the filled isolation trenches in a first horizontal direction; dielectric materials overlying the pillar structures, the filled isolation trenches, and the word lines; digit line contacts extending through a lower portion of the dielectric materials and into digit line contact regions of the semiconductive pillar structures; digit lines over and in contact with the digit line contacts and vertically extending through an upper portion of the dielectric materials, the digit lines extending in a second horizontal direction orthogonal to the first horizontal direction; additional dielectric materials over the digit lines and the dielectric materials; storage node contacts vertically extending through a lower portion of the additional dielectric materials, completely through the dielectric materials, and into storage node contact regions of the semiconductive pillar structures; and redistribution layer (RDL) structures over and in contact with the storage node contacts, the RDL structures vertically extending through an upper portion of the additional dielectric materials.
Yang teaches in Figs. 1, 4, 38 and related text a memory device ([0001]) comprising at least one microelectronic device structure (10; [0027]) comprising:
a base structure (16; [0028]) comprising semiconductive pillar structures (52; [0041]) horizontally separated from one another by filled isolation trenches (56, 58; [0042]);
word lines (28 (28a, 28b); [0031] and [0044]) extending through the semiconductive pillar structures and the filled isolation trenches in a first horizontal direction (horizontal direction in the top view of Fig. 1);
dielectric materials (204, 220; [0097]) overlying the pillar structures, the filled isolation trenches, and the word lines;
digit line contacts (70; [0049]) extending through a lower portion of the dielectric materials and into digit line contact regions (22; [0049]) of the semiconductive pillar structures;
digit lines (26 (68); [0048]) over and in contact with the digit line contacts and vertically extending through an upper portion of the dielectric materials, the digit lines extending in a second horizontal direction (vertical direction in the top view of Fig. 1) orthogonal to the first horizontal direction;
additional dielectric materials (214, 216; [0066] and [0077]) over the digit lines and the dielectric materials;
storage node contacts (77 (76); [0052]) vertically extending through a lower portion of the additional dielectric materials, completely through the dielectric materials, and into storage node contact regions (18, 20; [0052]) of the semiconductive pillar structures; and
redistribution layer (RDL) structures (32 (90, 92); [0026] and [0057]) over and in contact with the storage node contacts, the RDL structures vertically extending through an upper portion of the additional dielectric materials.
Lee and Yang are analogous art because they both are directed to dynamic random access memory (DRAM) and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee with the specified features of Yang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to provide a memory device comprising at least one microelectronic device structure comprising: a base structure comprising semiconductive pillar structures horizontally separated from one another by filled isolation trenches; word lines extending through the semiconductive pillar structures and the filled isolation trenches in a first horizontal direction; dielectric materials overlying the pillar structures, the filled isolation trenches, and the word lines; digit line contacts extending through a lower portion of the dielectric materials and into digit line contact regions of the semiconductive pillar structures; digit lines over and in contact with the digit line contacts and vertically extending through an upper portion of the dielectric materials, the digit lines extending in a second horizontal direction orthogonal to the first horizontal direction; additional dielectric materials over the digit lines and the dielectric materials; storage node contacts vertically extending through a lower portion of the additional dielectric materials, completely through the dielectric materials, and into storage node contact regions of the semiconductive pillar structures; and redistribution layer (RDL) structures over and in contact with the storage node contacts, the RDL structures vertically extending through an upper portion of the additional dielectric materials, as taught by Yang, in order to enable tight packing of the capacitors of a DRAM array, thereby enabling a higher level of integration (Yang: [0003]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M ALBRECHT whose telephone number is (571)272-7813. The examiner can normally be reached M-F 9:30 AM - 6:30 PM (CT).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M ALBRECHT/Primary Examiner, Art Unit 2811
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