CTNF 18/619,090 CTNF 100437 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim s 1-18 is/are objected to because of the following informalities: Claim 1 recites “first power delivery circuitry” in Line L7 but should read –a first power delivery circuitry --. Claim 2 recites “the first surface the second substrate” in Lines L3-4 but should read – the first surface of the second substrate --. Claim 10 recites “second power delivery circuitry” in Lines L1-2 but should read – the second power delivery circuitry --. Claim 11 recites “the one or more IC die” in Line L2 but should read – the one or more IC dies --. Claim 14 recites “first power delivery circuitry” in Line L8 but should read –a first power delivery circuitry --. Claim 14 recites “first support circuitry” in Line L11 but should read –a first support circuitry --. The balance of claims are objected to for being dependent upon an already objected claim . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-2, and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Desclos et al. (US 20240145452 A1-Desclos52) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18 . Regarding claim 1 , Desclos52 discloses a package device comprising: a first substrate (First substrate 64-Examiner's annotated Fig 1); an integrated circuit (IC) device mounted to a first surface of the first substrate (Integrated Circuit 62 electrically connected and mounted to first/ top surface of first substrate 64-Examiner's annotated Fig 1); a second substrate mounted to a second surface of the first substrate (Second substrate 60 mounted to second/ bottom surface of first substrate 64, including decoupling capacitor 10-Examiner's annotated Fig 1), wherein the first surface is opposite the second surface (Top/Bottom surfaces are opposite-Examiner's annotated Fig 1), and wherein the second substrate includes a decoupling capacitor (Second substrate 60 mounted to second/ bottom surface of first substrate 64, including decoupling capacitor 10-Examiner's annotated Fig 1); and first delivery circuitry mounted to the second substrate (First delivery circuitry 800 mounted to second substrate 60 by solder balls 48-Examiner's annotated Fig 1) and coupled to the IC device through the second substrate and the first substrate (First power delivery circuitry 800 electrically connected/ coupled to Integrated Circuit 66 through second substrate 60 and first substrate using path solder balls 48, interposer 77, first level coupling components 68-Examiner's annotated Fig 1, [0090]). Desclos52 does not explicitly disclose a package device comprising: First power delivery circuitry. NPLTDC18 teaches a package device comprising: First power delivery circuitry ( First power delivery circuitry PoL VR connected to Motherboard PCB-Fig 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Desclos52, as taught by NPLTDC18 for the purpose of providing lower complexity, higher reliability, and lower cost in terms of electrical design, manufacturing assembly yield, and thermal management (NPLTDS18: page 4 L1-14). PNG media_image1.png 815 1495 media_image1.png Greyscale Regarding claim 2 , Desclos52 and NPLTDC18 combination teaches all the elements of claim 1, as noted above. Desclos52 further discloses a package device comprising: wherein one or more connectors are mounted to a first surface of the second substrate and are connected to the first power delivery circuitry (Connectors 48 mounted on first/ bottom surface of Second substrate 80 and connected to the first power delivery circuitry 800-Examiner's annotated Fig 1), and wherein the decoupling capacitor is mounted to the first surface the second substrate (Decoupling capacitor 10 mounted on first/ bottom surface of Second substrate 80-Examiner's annotated Fig 1). Regarding claim 4 , Desclos52 and NPLTDC18 combination teaches all the elements of claim 1, as noted above. Desclos52 further discloses a package device comprising: a first connector mounted to the second substrate (First connectors mounted to the second substrate 60-Examiner's annotated Fig 1) and coupled to the first power delivery circuitry (First power delivery circuitry 800 electrically connected/ coupled to Integrated Circuit 66 through second substrate 60 and first substrate using path solder balls 48, interposer 77, connectors 68 -Examiner's annotated Fig 1, [0090]), wherein the first connector is mounted outside a perimeter of the IC device (First connectors 68 mounted to the second substrate 60, being outside the Perimeter of IC device shown as a dashed line rectangle-Examiner's annotated Fig 1) . 07-21-aia AIA Claim (s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Desclos et al. (US 20240145452 A1-Desclos52) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18 and further in view of Lane et al. (US 9331062 B1-Lane62) . Regarding claim 3 , Desclos52 discloses all the elements of claim 1, as noted above. Desclos52 does not disclose a package device comprising: wherein the decoupling capacitor is formed within one or more metal layers of the second substrate. Lane62 teaches a package device comprising: wherein the decoupling capacitor is formed within one or more metal layers of the second substrate ( decoupling capacitor 450 is formed within one or more metal layers 450-1/450-2 of the second substrate 10-Fig 6, C6L61-C4-L2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Desclos52, as taught by Lane62 for the purpose of reducing the routing complexity in the integrated circuit by separating the user signal routing from the power routing (Lane62: C2L63-C3L6) . 07-21-aia AIA Claim (s) 1, 5-6,8-9, 11-12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18 . Regarding claim 1 , Weng87 discloses a package device comprising: a first substrate (First substrate 190 with first surface 192 and second surface 196-Examiner's annotated Fig 1A); an integrated circuit (IC) device mounted to a first surface of the first substrate (IC 106/104 electrically connected and mounted to first/ top surface of first substrate 194-Examiner's annotated Fig 1A); a second substrate mounted to a second surface of the first substrate (Second substrate 128 with first surface 126 and second surface 122 mounted to second surface 196 of first substrate 190-Examiner's annotated Fig 1A), wherein the first surface is opposite the second surface (first surface 192 and second surface 196 are opposite-Examiner's annotated Fig 1A), and wherein the second substrate includes a decoupling capacitor (coupling capacitor 138 mounted to second substrate 128-Examiner's annotated Fig 1A, [0039]); and first delivery circuitry mounted to the second substrate (First delivery circuitry 142 of PCB 172 mounted to first surface 126 of second substrate 128 by solder balls 110 [0035]-Examiner's annotated Fig 1A) and coupled to the IC device through the second substrate and the first substrate (First power delivery circuitry 142 electrically connected/ coupled to Integrated Circuit 104/106 through second substrate 128 and first substrate 190 using circuitry 182, vias 144/146, circuitry 114-Examiner's annotated Fig 1A). Weng87 does not explicitly disclose a package device comprising: First power delivery circuitry. NPLTDC18 teaches a package device comprising: First power delivery circuitry ( First power delivery circuitry PoL VR connected to Motherboard PCB-Fig 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Weng87, as taught by NPLTDC18 for the purpose of providing lower complexity, higher reliability, and lower cost in terms of electrical design, manufacturing assembly yield, and thermal management (NPLTDS18: page 4 L1-14). PNG media_image2.png 985 1623 media_image2.png Greyscale Regarding claim 5 , Weng87 and NPLTDC18 combination teaches all the elements of claim 1, as noted above. Weng87 further discloses a package device comprising: wherein the first power delivery circuitry is mounted to a first surface of the second substrate (First power delivery circuitry 142 of PCB 172 mounted to first surface 126 of second substrate 128 by solder balls 110-[0035], Examiner's annotated Fig 1), and a second surface of the second substrate is mounted to the second surface of the first substrate (Second substrate 128 with first surface 126 and second surface 122 mounted to second surface 196 of first substrate 190-Examiner's annotated Fig 1A). Regarding claim 6 , Weng87 and NPLTDC18 combination teaches all the elements of claim 5, as noted above. Weng87 further discloses a package device comprising: wherein first connectors are disposed between the first surface of the first substrate and the IC device (First connectors 108 mounted to the first surface 192 of second substrate 190, disposed between the first surface 192 of first substrate 190 and IC device 106 -Examiner's annotated Fig 1A), and second connectors are disposed between the second surface of the first substrate and the second surface of the second substrate (Second connectors disposed between the second surface 196 of first substrate 190 and second surface 122 of second substrate 128-Examiner's annotated Fig 1A). Regarding claim 8 , Weng87 and NPLTDC18 combination teaches all the elements of claim 6, as noted above. Weng87 further discloses a package device comprising: wherein a first one of first connectors is coupled to a first one of the second connectors through a first via in the first substrate (First on of first connectors 108 electrically connected so coupled to a first one of the second connectors through a first via 144/146 in the first substrate 190-Examiner's annotated Fig 1A, [0021]), and wherein the first power delivery circuitry is coupled to the first one of the second connectors through one or more vias and one or more metal lines within the second substrate (First power delivery circuitry 142 electrically connected so coupled to a first one of the second connectors through vias/metal line of circuitry 182 within the second substrate 128-Examiner's annotated Fig 1A, [0035]). Regarding claim 9 , Weng87 and NPLTDC18 combination teaches all the elements of claim 8, as noted above. Weng87 further discloses a package device wherein the first one of the first connectors is vertically aligned with the first one of the second connectors (first one of first connectors 108 and first one of the second connectors are vertically aligned-Examiner's annotated Fig 1A). Regarding claim 11 , Weng87 and NPLTDC18 combination teaches all the elements of claim 1, as noted above. Weng87 further discloses a package device wherein the IC device includes one (IC device 104/106 including one IC die 104-[0018] L5-6) or more IC dies vertically mounted on each other, wherein the one (IC die 104 including a high bandwidth memory device-[0026] L8-9) or more IC die include a high bandwidth memory device. Regarding claim 12 , Weng87 and NPLTDC18combination teaches all the elements of claim 1, as noted above. Weng87 further discloses a package device wherein the IC device includes one (IC device 104/106 include IC die 104 mounted on interposer 190-[0036] L7, Examiner's annotated Fig 1A) or more IC dies mounted to an interposer. Regarding claim 19 , Weng87 discloses a method of forming a package device ([0017] L1-2), the method comprising: mounting a delivery circuitry mounted to the second substrate (delivery circuitry 142 of PCB 172 mounted to first surface 126 of second substrate 128 by solder balls 110-[0018] L13-16, [0035], Examiner's annotated Fig 1A) providing a decoupling capacitor to the first substrate (Decoupling capacitor 130 mounted on First substrate 190 so providing 130 to the first substrate 190-Examiner's annotated Fig 1A, [0021] L1-4, [0025] L1-4); and mounting a second surface of the first substrate to a first surface of a second substrate (Second substrate 128 with first surface 126 mounted to second surface 196 of first substrate 190 with the second connectors-Examiner's annotated Fig 1A), wherein an integrated circuit device is mounted to a second side of the second substrate (Integrated circuit 120 connected to coupling capacitor 138 mounted on second surface 122 so integrated circuit 120 mounted to second surface 122 of second substrate 128-Examiner's annotated Fig 1A), and wherein the IC device is coupled to the power delivery circuitry through the first substrate and the second substrate (First power delivery circuitry 142 electrically connected/ coupled to Integrated Circuit 104/106 through second substrate 128 and first substrate 190 using circuitry 182, vias 144/146, circuitry 114-Examiner's annotated Fig 1A). Weng87 does not explicitly disclose a method of forming a package device comprising First power delivery circuitry. NPLTDC18 teaches a method of forming a package device comprising First power delivery circuitry ( First power delivery circuitry PoL VR connected to Motherboard PCB-Fig 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a package device of Weng87, as taught by NPLTDC18 for the purpose of providing lower complexity, higher reliability, and lower cost in terms of electrical design, manufacturing assembly yield, and thermal management (NPLTDS18: page 4 L1-14) . PNG media_image2.png 985 1623 media_image2.png Greyscale 07-21-aia AIA Claim (s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US20240178087A1 from IDS -Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18 and further in view of Roth et al. (US 20230261572 A1-Roth72) . Regarding claim 13 , Weng87 and NPLTDS18 combination teaches all the elements of claim 8, as noted above. Weng87 and NPLTDS18 combination does not teach a package device wherein a first heatsink is mounted to the IC device and a second heatsink is mounted to the first power delivery circuitry. Roth72 teaches a package device wherein a first heatsink is mounted to the IC device (Heatsink 304 mounted to IC device 102/302-Fig 3, [0050] L16-19) and a second heatsink is mounted to the first power delivery circuitry (first power delivery circuitry 125 configured to receive heatsink so a second heatsink is mounted to the first power delivery circuitry-[0047] L3-5). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Weng87 in view of Declos52, as taught by Roth72 for the purpose of facilitating the dissipation of heat within the semiconductor structure (Roth72: [0050]) . 07-21-aia AIA Claim (s) 14, 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US20240178087A1 from IDS -Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18 and further in view of Kuan et al (US 20220077065 A1-Kuan65) . Regarding claim 14 , Weng87 discloses a package device comprising: a package device (Chip package-Title) comprising: a first substrate (First substrate 190 with first surface 192 and second surface 196-Examiner's annotated Fig 1A); an integrated circuit (IC) device mounted to a first surface of the first substrate (IC 106/104 electrically connected and mounted to first/ top surface of first substrate 194-Examiner's annotated Fig 1A); a second substrate mounted to a second surface of the first substrate (Second substrate 128 with first surface 126 and second surface 122 mounted to second surface 196 of first substrate 190-Examiner's annotated Fig 1A), wherein the first surface is opposite the second surface (first surface 192 and second surface 196 are opposite-Examiner's annotated Fig 1A), and wherein the second substrate includes a decoupling capacitor (coupling capacitor 138 mounted to second substrate 128-Examiner's annotated Fig 1A, [0039]); and first delivery circuitry mounted to the second substrate (First delivery circuitry 142 of PCB 172 mounted to first surface 126 of second substrate 128 by solder balls 110 [0035]-Examiner's annotated Fig 1A) and coupled to the IC device through the second substrate and the first substrate (First power delivery circuitry 142 electrically connected/ coupled to Integrated Circuit 104/106 through second substrate 128 and first substrate 190 using circuitry 182, vias 144/146, circuitry 114-Examiner's annotated Fig 1A). Weng87 does not explicitly disclose a package device comprising: First power delivery circuitry. NPLTDC18 teaches a package device comprising: First power delivery circuitry ( First power delivery circuitry PoL VR connected to Motherboard PCB-Fig 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Weng87, as taught by NPLTDS18 for the purpose of providing lower complexity, higher reliability, and lower cost in terms of electrical design, manufacturing assembly yield, and thermal management (NPLTDC18: page 4 L1-14). Weng87 and NPLTDC18 combination does not teach a package device comprising: first support circuitry mounted to the first surface of the first substrate and electrically connected to the IC device, wherein the first support circuitry is configured to receive data signals from the IC device. Kuan65 teaches a package device comprising: first support circuitry mounted to the first surface of the first substrate (First support circuitry 320 mounted to first/ top surface of first substrate Package, electrically connected to IC device 310/312/Chip, and configured for data signal transmission-Examiner's annotated Fig 3, [0023] L20-34) and electrically connected to the IC device (First support circuitry 320 mounted to first/ top surface of first substrate Package, electrically connected to IC device 310/312/Chip, and configured for data signal transmission-Examiner's annotated Fig 3, [0023] L20-34), wherein the first support circuitry is configured to receive data signals from the IC device (First support circuitry 320 mounted to first/ top surface of first substrate Package, electrically connected to IC device 310/312/Chip, and configured for data signal transmission-Examiner's annotated Fig 3, [0023] L20-34). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Weng87 in view of NPLTDC18, as taught by Kuan65 for the purpose of reducing I/O pin count because chiplets and devices may be interconnected through the two-step interposer module mitigating AC noise, thus aiding in increased signal transmission data-rate, computing core performance, or graphics Fmax performance gain (Kuan65: [0041]). PNG media_image3.png 985 1623 media_image3.png Greyscale PNG media_image4.png 664 1175 media_image4.png Greyscale Regarding claim 16 , Weng87, NPLTDC18, and Kyan65 combination teaches all the elements of claim 14, as noted above. Weng87 further discloses an IC system wherein the first power delivery circuitry is mounted to a first surface of the second substrate (First power delivery circuitry 142 of PCB 172 mounted to first surface 126 of second substrate 128 by solder balls 110-[0035], Examiner's annotated Fig 1), and a second surface of the second substrate is mounted to the second surface of the first substrate (Second substrate 128 with first surface 126 and second surface 122 mounted to second surface 196 of first substrate 190-Examiner's annotated Fig 1A), wherein first connectors are disposed between the first surface of the first substrate and the IC device (First connectors 108 mounted to the first surface 192 of second substrate 190, disposed between the first surface 192 of first substrate 190 and IC device 106 -Examiner's annotated Fig 1A), and second connectors are disposed between the second surface of the first substrate and the second surface of the second substrate (Second connectors disposed between the second surface 196 of first substrate 190 and second surface 122 of second substrate 128-Examiner's annotated Fig 1A), and wherein the first one of the first connectors is vertically aligned with the first one of the second connectors (first one of first connectors 108 and first one of the second connectors are vertically aligned-Examiner's annotated Fig 1A). Regarding claim 18 , Weng87, NPLTDS18, and Kyan65 combination teaches all the elements of claim 14, as noted above. Weng87 further discloses an IC system wherein the IC device includes one (IC device 104/106 including one IC die 104-[0018] L5-6) or more IC dies vertically mounted on each other, wherein the one (IC die 104 including a high bandwidth memory device-[0026] L8-9) or more IC die include a high bandwidth memory device, wherein the one (IC die 104 including a high bandwidth memory device-[0026] L8-9) or more IC die include a high bandwidth memory device, or wherein the IC device includes one (IC device 104/106 include IC die 104 mounted on interposer 190-[0036] L7, Examiner's annotated Fig 1A) or more IC dies mounted to an interposer . 07-21-aia AIA Claim (s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18, in view of Kuan et al (US 20220077065 A1-Kuan65), and further in view of Desclos et al. (US 20240145452 A1-Desclos52) . Regarding claim 15 , Weng87, NPLTDC18, and Kyan65 combination teaches all the elements of claim 14, as noted above. Weng87, NPLTDC18, and Kyan65 combination does not teach an IC system wherein at least one of: one or more connectors are mounted to a first surface of the second substrate, and wherein the decoupling capacitor is mounted to the first surface the second substrate, or the decoupling capacitor is formed within one or more metal layers of the second substrate. Desclos52 teaches an IC system wherein at least one of: one or more connectors are mounted to a first surface of the second substrate and are connected to the first power delivery circuitry (Connectors 48 mounted on first/ bottom surface of Second substrate 80 and connected to the first power delivery circuitry 800-Examiner's annotated Fig 1), and wherein the decoupling capacitor is mounted to the first surface the second substrate (Decoupling capacitor 10 mounted on first/ bottom surface of Second substrate 80-Examiner's annotated Fig 1) or the decoupling capacitor is formed within one or more metal layers of the second substrate. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package device of Weng87 in view of NPLTDC18, and further in view of Kuan65, as taught by Desclos52 for the purpose of maintaining a constant voltage by employing decoupling capacitors (Desclos52: [0002]) . 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18, and further in view of Lane et al. (US 9331062 B1-Lane62) . Regarding claim 20 , Weng87 and NPLTDC18 combination teaches all the steps of claim 19, as noted above. Weng87 and NPLTDC18 combination does not teach a method of forming a package device further comprising at least one of: mounting the decoupling capacitor on a second surface of the first substrate; and forming the decoupling capacitor within a metal layer of the first substrate. Lane62 teaches a method of forming a package device further comprising at least one of: mounting the decoupling capacitor on a second surface of the first substrate; and forming the decoupling capacitor within a metal layer of the first substrate (decoupling capacitor 450 is formed within one or more metal layers 450-1/450-2 of the first substrate 10-Fig 6, C6L61-C4-L2). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of forming a package device of Desclos52, as taught by Lane62 for the purpose of reducing the routing complexity in the integrated circuit by separating the user signal routing from the power routing (Lane62: C2L63-C3L6) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7, 10, and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter : Regarding claim 7 , the prior art of record does not teach or suggest a package device, namely “wherein a first connector and a second connector of the first connectors are respectively associated with a power supply pin and a ground pin of the IC device, and a third connector and a fourth connector of the second connectors are respectively configured to output a power supply signal and a ground voltage, and wherein the first connector is aligned with the third connector and the second connector is aligned with the fourth connector”. References such as Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18, teaches a package device, but does not teach or suggest a package device, namely “wherein a first connector and a second connector of the first connectors are respectively associated with a power supply pin and a ground pin of the IC device, and a third connector and a fourth connector of the second connectors are respectively configured to output a power supply signal and a ground voltage, and wherein the first connector is aligned with the third connector and the second connector is aligned with the fourth connector ”, in combination with other claimed elements. Regarding claim 10 , the prior art of record does not teach or suggest a package device, namely “wherein the second power delivery circuitry is coupled to the second one of the second connectors, and wherein the second one of the first connectors is further coupled to the second one of the second connectors through one or more metal layers within the first substrate”. References such as Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18, teaches a package device, but does not teach or suggest a package device, namely “wherein the second power delivery circuitry is coupled to the second one of the second connectors, and wherein the second one of the first connectors is further coupled to the second one of the second connectors through one or more metal layers within the first substrate ”, in combination with other claimed elements. Regarding claim 17 , the prior art of record does not teach or suggest an IC system, namely “wherein a first connector and a second connector of first connectors are respectively associated with a power supply pin and a ground pin of the IC device, and a third connector and a fourth connector of the second connectors are respectively configured to output a power supply signal and a ground voltage, and wherein the first connector is aligned with the third connector and the second connector is aligned with the fourth connector”. References such as Weng et al. (US20240178087A1 from IDS-Weng87) in view of "VERTICAL POWER DELIVERY STRUCTURE FOR ULTRA-HIGH CURRENT APPLICATIONS", Technical Disclosure Commons, (September 26, 2018) from IDS hereafter NPLTDC18, and further in view of Kuan et al (US 20220077065 A1-Kuan65, teaches an IC system, but does not teach or suggest an IC system, namely “wherein a first connector and a second connector of first connectors are respectively associated with a power supply pin and a ground pin of the IC device, and a third connector and a fourth connector of the second connectors are respectively configured to output a power supply signal and a ground voltage, and wherein the first connector is aligned with the third connector and the second connector is aligned with the fourth connector ”, in combination with other claimed elements. The balance of the claims are allowable for at least the above-stated reasons . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Chandrasekar et al. (US 9129935 B1-Chandrasekar35) teaches a package device (title) comprising: a first substrate (108-Fig 4); an integrated circuit (IC) device mounted to a first surface of the first substrate (130 on top surface of 108-Fig 3) ; a second substrate mounted to a second surface of the first substrate (122/126 mounted on bottom surface of 108-Fig 3, Fig 4), wherein the first surface is opposite the second surface (Top/Bottom surfaces are opposite-Fig 3), and wherein the second substrate includes a decoupling capacitor (122 including decoupling capacitor 106-Fig 4); and first power delivery circuitry (102-Fig 2) and coupled to the IC device(102 coupled to IC 10-1/ 10-2-Fig 2). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NATHALIE R. FAYETTE Examiner Art Unit 2812 /NATHALIE R FAYETTE/Examiner, Art Unit 2812 04/22/2026 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812 Application/Control Number: 18/619,090 Page 2 Art Unit: 2812 Application/Control Number: 18/619,090 Page 3 Art Unit: 2812 Application/Control Number: 18/619,090 Page 4 Art Unit: 2812 Application/Control Number: 18/619,090 Page 5 Art Unit: 2812 Application/Control Number: 18/619,090 Page 6 Art Unit: 2812 Application/Control Number: 18/619,090 Page 7 Art Unit: 2812 Application/Control Number: 18/619,090 Page 8 Art Unit: 2812 Application/Control Number: 18/619,090 Page 9 Art Unit: 2812 Application/Control Number: 18/619,090 Page 10 Art Unit: 2812 Application/Control Number: 18/619,090 Page 11 Art Unit: 2812 Application/Control Number: 18/619,090 Page 12 Art Unit: 2812 Application/Control Number: 18/619,090 Page 13 Art Unit: 2812 Application/Control Number: 18/619,090 Page 14 Art Unit: 2812 Application/Control Number: 18/619,090 Page 15 Art Unit: 2812 Application/Control Number: 18/619,090 Page 16 Art Unit: 2812 Application/Control Number: 18/619,090 Page 17 Art Unit: 2812 Application/Control Number: 18/619,090 Page 18 Art Unit: 2812 Application/Control Number: 18/619,090 Page 19 Art Unit: 2812 Application/Control Number: 18/619,090 Page 20 Art Unit: 2812 Application/Control Number: 18/619,090 Page 21 Art Unit: 2812 Application/Control Number: 18/619,090 Page 22 Art Unit: 2812 Application/Control Number: 18/619,090 Page 23 Art Unit: 2812 Application/Control Number: 18/619,090 Page 24 Art Unit: 2812
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