DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 6, 8-9, 11-12, 14, 16 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon (US Pub. No. 2018/0188311).
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Regarding claim 1, Kwon discloses [see Figs. 9-10] a test apparatus comprising: a sampling circuit (measuring equipment 200 in Fig. 4 or measuring unit 310) configured to output, during a first test period, a first test input signal to a first circuit block (functional block 110) included in each of a plurality of semiconductor devices (semiconductor device 100) to be tested, and receive a first test output signal outputted from the first circuit block (110) [see paragraphs [0082] & [0109] for details]; and a test control circuit (calculation unit 320) configured to output, during a second test period, a second test input signal having a test frequency set for each of the plurality of semiconductor devices (100), corresponding to an output frequency [see paragraphs [0087]-[0088] & [0110] for details] or an output current value of the first test output signal to a second circuit block included in each of the plurality of semiconductor devices, and perform a test on each of the plurality of semiconductor devices (100).
Regarding claim 2, Kwon discloses wherein the test control circuit (320) classifies each of the plurality of semiconductor devices (100) into one of N number of preset groups based on the output frequency or the output current value of the first test output signal, and performs a test on each of the plurality of semiconductor devices (100) using the second test input signal having the test frequency set for each of the N number of preset groups, where N is a natural number 2 or more [see paragraphs [0067]-[0069] and [0110] for details].
Regarding claim 4, Kwon discloses wherein the test frequency is set in proportion to the output frequency [see paragraphs [0073]-[0075] & [0077] for details] or the output current value of the first test output signal.
Regarding claim 6, Kwon discloses wherein: an input frequency of the first test input signal inputted to a first semiconductor device (100) among the plurality of semiconductor devices (100) is equal to an input frequency of the first test input signal inputted to a second semiconductor device (100); and the test frequency of the second test input signal inputted to the first semiconductor device (100) is different from the test frequency of the second test input signal inputted to the second semiconductor device (100) [see paragraphs [0073]-[0075] & [0077] for details].
Regarding claim 8, Kwon discloses wherein: the output frequency or the output current value of the first test output signal of a first semiconductor device (100) among the plurality of semiconductor devices (100) is greater than the output frequency or the output current value of the first test output signal of a second semiconductor device (100); and the test frequency of the second test input signal inputted to the first semiconductor device (100) is greater than the test frequency of the second test input signal inputted to the second semiconductor device (100) [see paragraphs [0073]-[0075] & [0077] for details].
Regarding claim 9, Kwon discloses wherein: the output frequency or the output current value of the first test output signal of a third semiconductor device (100) among the plurality of semiconductor devices (100) is less than the output frequency or the output current value of the first test output signal of the first semiconductor device, and is greater than the output frequency or the output current value of the first test output signal of the second semiconductor device (100); and the test frequency of the second test input signal inputted to the third semiconductor device (100) is identical to the test frequency of the second test input signal inputted to the first semiconductor device (100) or the test frequency of the second test input signal inputted to the second semiconductor device (100).
Regarding claim 11, Kwon discloses a cache memory [not shown but see paragraphs [0106] & [0114] for details] configured to store the output frequency or the output current value of the first test output signal obtained by the sampling circuit.
Regarding claim 12, Kwon discloses wherein the first circuit block (110) includes a process detector circuit block [see paragraphs [0028]-[0031], [0110] & [0113] for details], and the second circuit block includes a scan test circuit block.
Regarding claim 14, Kwon discloses [see Figs. 9-10] a semiconductor device (semiconductor device 100) comprising: a first circuit block (function block 110) configured to externally receive a first test input signal and output a first test output signal during a first test period [via measuring equipment 200 in Fig. 4 or measuring unit 310]; and a second circuit block (function block 120) configured to externally receive a second test input signal which has a test frequency set corresponding to an output frequency [measuring equipment 200 in Fig. 4 or measuring unit 310] or an output current value of the first test output signal, during a second test period.
Regarding claim 16, Kwon discloses wherein the test frequency is set in proportion to the output frequency [see paragraphs [0073]-[0075] & [0077] for details] or the output current value of the first test output signal.
Regarding claim 19, Kwon discloses a method for testing a semiconductor chip (semiconductor device 100), the method comprising: transmitting [via measuring equipment 200 in Fig. 4 or measuring unit 310], during a first test period, a first test input signal to a first circuit block (function block 110) included in each of a plurality of semiconductor devices (100); receiving [via measuring equipment 200 in Fig. 4 or measuring unit 310] a first test output signal outputted from the first circuit block (110); classifying [via calculation unit 320] each of the plurality of semiconductor devices (100) into one of N number of preset groups based on an output frequency or an output current value of the first test output signal; and transmitting [via measuring equipment 200 in Fig. 4 or measuring unit 310], during a second test period, a second test input signal which has a test frequency set for each of the N number of preset groups to a second circuit block (functional block 120) included in each of the plurality of semiconductor devices (100), where N is a natural number 2 or more.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 for details.
Allowable Subject Matter
Claims 3, 5, 7, 10, 13, 15, 17-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding claims 3 and 15, the primary reason for the allowance of the claim is due to a length of the first test period is less than a length of the second test period.
Regarding claims 5 and 17, the primary reason for the allowance of the claim is due to a length of the second test period is inversely proportional to the output frequency or the output current value of the first test output signal.
Regarding claim 7, the primary reason for the allowance of the claim is due to a length of the first test period for a first semiconductor device among the plurality of semiconductor devices is equal to a length of the first test period for a second semiconductor device; and a length of the second test period for the first semiconductor device is different from a length of the second test period for the second semiconductor device.
Regarding claims 10 and 18, the primary reason for the allowance of the claim is due to wherein the first test input signal comprises a first test clock signal, and the second test input signal comprises a second test clock signal and a test data signal.
Regarding claim 13, the primary reason for the allowance of the claim is due to the first circuit block includes an electrical parameter measurement circuit block, and the second circuit block includes a scan test circuit block.
Regarding claim 20, the primary reason for the allowance of the claim is due to a length of the first test period is less than a length of the second test period, and a deviation of the first test period for each of the plurality of semiconductor devices is less than a deviation of the second test period for each of the plurality of semiconductor devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERMELE M HOLLINGTON whose telephone number is (571)272-1960. The examiner can normally be reached Mon-Fri 7:00am-3:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee E Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JERMELE M HOLLINGTON/ Primary Examiner, Art Unit 2858