Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-8 in the reply filed on 7/7/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Straight-Path Semiconductor.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 1 and 8 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitations "testing path that is...straight" in claim 1 and "testing path. Claims 2-7 are also rejected because they depend directly from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US20220077008A1) in view of Jiang et al. (CN116230575B) and Choi et al. (US20210175133A1).
Regarding Claim 1:
Huang discloses a semiconductor test structure (Fig. 4), comprising:
a substrate (Fig. 1 element 30) comprising a testing area (element 20), the testing area comprising an isolation area (Fig. 4 element 250) and a plurality of active areas (Fig. 2 elements 210) spaced apart by the isolation area (paragraph 32), wherein each active area has a major axis (paragraphs 33) and has a first end [head end] and a second end (tail end; paragraphs 28 and 31-37);
a plurality of contacts (Fig. 4 elements 221/222) disposed on the active areas (elements 210), wherein each contact corresponds to the first end (element 221) or the second end of each active area (element 222, paragraph 31-33);
a plurality of connecting lines (Figs. 2/4 elements 220/223) disposed between the active areas (paragraph 28), wherein the active areas, the contacts, and the connecting lines form a testing path that is substantially straight (Fig. 2, paragraphs 35-37 and 62).
However, Huang does not explicitly disclose an input or an output disposed at opposite sides of the testing area. Nor does Huang disclose a plurality of top electrodes disposed on the contacts wherein two adjacent top electrodes are electrically connected by a connecting line.
Jiang discloses an analogous semiconductor test structure (Fig. 8), comprising a plurality of active areas (elements 111), an input (element 5) and an output (element 6) disposed at opposite sides of the testing area (paragraph 93), wherein first ends of the active area (Fig. 2 elements 21/1101) face toward the input and second ends of the active area (element 22/1202) face toward the output. But Jiang does not explicitly disclose a plurality of top electrodes disposed on the active areas.
Choi discloses an analogous test pattern structure (Fig. 7 elements 49A/B), comprising of a plurality of active areas (Fig. 2 element 41), a plurality of contacts (elements 42/43/44), and a plurality of top electrodes (element 45) disposed on the contacts, wherein each top electrode corresponds to one of the contacts (paragraphs 37 and 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang further in view of Jiang and Choi to explicitly include an input and output disposed at opposite sides of the testing area, wherein the first ends face toward the input and the second ends face toward output. Further, a plurality of top electrodes – included in the testing path – disposed on the contacts, wherein adjacent two top electrodes are electrically connected by one of the connecting lines because both are directed to analogous test structures for memory devices. Doing so improves the accuracy of resistance testing and the efficiency of the overall manufacturing process (Jiang, paragraphs 2, 36, and 54 and Choi, paragraphs 3-5).
Regarding Claim 2:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, wherein Huang further discloses each contact (Fig. 4 element 221/222) is in direct contact with the first ends or the second ends (paragraph 33).
Regarding Claim 3:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, but neither Huang nor Jiang explicitly disclose where each top electrode is in direct contact with a corresponding contact.
Choi, however, discloses an analogous test pattern structure (Fig. 7 elements 49A/B), wherein each top electrode (Fig. 2 element 45) is in direct contact with one of the contacts corresponding (elements 42/43/44, paragraphs 37 and 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang and Jiang further in view of Choi to explicitly include where each top electrode is in direct with one of the contacts – correspondingly – because both are directed to analogous test structures in semiconductor devices. Doing so allows for more precise electrical testing efforts (Choi, paragraphs 2-4).
Regarding Claim 4:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, neither Huang nor Choi explicitly disclose where the input is connected to one of the top electrodes on the testing path closest to the input.
Jiang, however, discloses an analogous semiconductor test structure (Fig. 8), wherein the input (Fig. 2 element 5) is connected to one of the first ends of an active region (element 1101) and a corresponding contact (element 21) on the testing path closest to the input (paragraphs 93-94).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang and Choi further in view of Jiang to explicitly include wherein the input is connected to one of the top electrodes on the testing path closest to the input because both are directed to analogous contact resistance test structures. Doing so aids in producing more accurate resistance measurements (Jiang, paragraphs 36, 54, and 67).
Regarding Claim 5:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, but neither Huang nor Choi explicitly disclose where the output is connected to one of the top electrodes on the testing path closest to the output.
Jiang, however, discloses an analogous semiconductor test structure (Fig. 8), wherein the output (Fig. 2 element 6) is connected to one of the second ends of an active region (element 1202) and a corresponding contact (element 22) on the testing path closest to the output (paragraphs 93-94).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang and Choi further in view of Jiang to explicitly include wherein the output is connected to one of the top electrodes on the testing path closest to the output because both are directed to analogous contact resistance test structures. Doing so aids in producing more accurate resistance measurements (Jiang, paragraphs 36, 54, and 67).
Regarding Claim 6:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, wherein Huang further discloses the connecting lines (Fig. 4 elements 220/223) are disposed on a top surface of the contacts (paragraph 50) but does not explicitly disclose where the top electrodes, connecting lines, input and output are at the same level.
Jiang, however, discloses an analogous semiconductor test structure (Fig. 8), wherein the input (Fig. 2 element 5) and output (element 6) are disposed on a top surface of corresponding contacts (elements 2, paragraph 92).
Choi discloses an analogous test pattern structure (Fig. 7 elements 49A/B), wherein the top electrodes (Fig. 2 elements 45) are disposed on a top surface of corresponding contacts (elements 42/43/44, paragraph 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang further in view of Jiang and Choi to explicitly include wherein the top electrodes, the connecting lines, the input, and the output are at a same level because both are directed to analogous test structures for memory devices. Doing so improves the accuracy of resistance testing and the efficiency of the overall manufacturing process (Jiang, paragraphs 2, 36, and 54 and Choi, paragraph 3-5).
Regarding Claim 7:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, but neither Huang nor Jiang explicitly disclose where the contacts and the top electrodes are configured to be one to one.
Choi, however, discloses an analogous test pattern structure (Fig. 7 elements 49A/B), wherein a configuration between the contacts (Fig. 2 elements 42/43/44) and top electrodes is one to one (element 45, paragraphs 37 and 43).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure describe in Huang and Jiang further in view of Choi to explicitly include wherein a configuration between the contacts and the top electrodes is one to one because both are directed to analogous test structures in semiconductor devices. Doing so allows for more precise electrical testing efforts (Choi, paragraphs 2-4).
Regarding Claim 8:
The combination of Huang, Jiang, and Choi disclose a semiconductor test structure according to claim 1, wherein Huang further discloses the testing path (Fig. 2 element L2) is substantially parallel to the major axes of the active areas (paragraphs 32-37 and 62).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang et al. (US 20220077009 A1), Lee et al. (US 20090050886 A1).
Conclusion
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/Chloë E Benton/Examiner, Art Unit 2899
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