Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant's arguments filed November 12th, 2025, regarding the double patenting rejections and rejection of claim 98 and its dependents have been fully considered but they are not persuasive.
Applicant claims that the previous nonstatutory double patenting rejections should be withdrawn in view of the concurrently filed terminal disclaimer, however, Examiner notes that no terminal disclaimer has been received or filed in this application, and so the rejections will be maintained.
Regarding the rejection of claim 98, Applicant argues that Isobe and Eisen fail to teach the claimed limitations as Isobe “do[es] not show any MPs [memory ports]”, and that Eisen “merely discloses an address generating (AGEN) bus” but fails to teach “an address calculation unit configured to generate respective memory addresses”.
In response to the above argument, Examiner respectfully disagrees. Identity of terminology is not required for anticipation, as per MPEP §2131. Isobe Figure 1 shows a clear connection between the memory 132 contained within configurable circuit 130 and the communication unit 101, which controls the reading and writing of data to and from the memory 132 (Isobe 7:26-32). The claims do not recite any additional details of the “memory ports” beyond their use to “access” the memory by the PEs, which is clearly disclosed by Isobe. Eisen similarly discloses in the previously cited paragraphs that the execution clusters handle “address generation” (Eisen [0025]), and later paragraphs explicitly state that hardware within the exemplary execution slices of the reconfigurable processing elements “may be provided for address computation” (Eisen [0030]). Therefore, Applicant’s arguments are not considered persuasive and the rejections are maintained.
2. Applicant’s arguments, filed November 12th, 2025, with respect to the rejection of claim 1 and its dependents have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Tanaka (US 2008/0168465).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
3. Claims 1-23 and 98-115 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-16 of U.S. Patent No. 11,226,927 and claims 1-16 of U.S. Patent No. 11,971,847. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant application would be anticipated by those of ‘927 and ‘847.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tanaka (US 2008/0168465).
Regarding claim 1, Tanaka teaches a processor, comprising:
a plurality of processing elements (PEs) (Fig 1, PEs & DRPs) each comprising a configuration buffer (Fig 2, [0052], configuration buffer CFGBUF in each DRP);
a sequencer coupled to the configuration buffer of each of the plurality of the PEs and configured to distribute one or more PE configurations to the configuration buffer (Figs, 1, 4-5, [0054], [0056-0057], [0072-0073], storing and transferring configurations to configuration buffers of a PE under control of sub-processor SPU); and
a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration ([0054-0055], storing arithmetic operation results in local memory, local memory used as input to next data processing task [0041], determining next task to be performed & [0045-0046], external memory available to all processing elements).
Regarding claim 2, Tanaka teaches the processor of claim 1, further comprising a plurality of switch boxes coupled to the sequencer to receive switch box configurations from the sequencer, each of the plurality of switch boxes being associated with a respective PE of the plurality of PEs and configured to provide input data switching for the respective PE according to the switch box configurations (Figs 1-2, [0053-0054], configuration manager to receive configurations for each reconfigurable array from the SPU, [0054], [0078], configurations are switched by CFGM operation to handle task & data switching).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Isobe (US 7,529,901).
Regarding claim 3, Tanaka teaches the processor of claim 2. Tanaka fails to teach wherein the plurality of switch boxes and their associated PEs are arranged in a plurality of columns, a first switch box in a first column of the plurality of columns is coupled between the gasket memory and a first PE in the first column of the plurality of columns, and a second PE in a last column of the plurality of columns is coupled to a gasket memory.
Isobe teaches a processor wherein a plurality of switch boxes and associated PEs are arranged in a plurality of columns, a first switch box in a first column of the plurality of columns is coupled between the gasket memory and a first PE in the first column of the plurality of columns, and a second PE in a last column of the plurality of columns is coupled to a gasket memory (Fig 1, 4:43-5:4, 6:30-33, input data dividing units and retiming selection buffers coupled to memory and sequencing buffers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tanaka and Isobe to utilize a column based arrangement for the parallel processing apparatus. While Tanaka does not disclose any specific implementation details of how the multiple reconfigurable processors and their reconfigurable arrays are layed out, utilizing a simple column and row layout as disclosed by Isobe would be an obvious means of providing data parallelism and a standard dataflow scheme as is routine in the microprocessor art. As both Tanaka and Isobe disclose parallel reconfigurable processing systems, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 4, the combination of Tanaka and Isobe teaches the processor of claim 3, further comprising: 3Application No.Attorney Docket No. 6603-0006CONa memory unit for providing data storage for the plurality of PEs; and a plurality of memory ports each arranged in a separate column of the plurality of columns for the plurality of PEs to access the memory unit (Isobe Fig 1, memory 132 & 7:26-35, Tanaka Fig 2).
Regarding claim 5, the combination of Tanaka and Isobe teaches the processor of claim 4, further comprising a plurality of inter-column switch boxes (ICSBs) each comprising a configuration buffer configured to store ICSB configurations, the plurality of ICSBs being configured to provide data switching between neighboring columns of the plurality of columns according to the ICSB configurations (Isobe Fig 1, processed data selection units 111 & 112).
6. Claims 6-10 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka and Isobe in view of Duluk et al (US 2013/0268942, herein Duluk).
Regarding claim 6, the combination of Tanaka and Isobe teaches the processor of claim 5, wherein each of the plurality of memory ports (MPs) comprises a configuration buffer to store MP configurations (configuration buffers 121, 6:53-67).
Tanaka and Isobe fail to teach wherein the memory ports are configured to operate in a private access mode or a shared access mode during one MP configuration.
Duluk teaches a processor wherein memory ports of a reconfigurable processing element are configured to operate in a private access mode or a shared access mode during one MP configuration ([0103], reconfiguring PPUs & [0053], [0061], [0071], configuring memory to be shared between thread arrays).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tanaka and Isobe with Duluk to utilize shared memory access in the parallel processor. While Isobe only discloses the exemplary reconfigurable parallel processor as each processing element utilizing its own distinct memory, Isobe does disclose the communication unit retrieving information from outside the processor to configure the processing elements (Isobe 7:8-21). Therefore, utilizing an external shared memory when appropriate for programs which share a thread array indicator, as taught by Duluk, would allow for the processor to have a distinct shared memory space rather than continually transferring the necessary data between local memories of each configurable element. As threaded execution is a routine and conventional aspect of the microprocessor art, this would merely entail a combination of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 7, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 6, wherein a piece of data stored in the memory unit is accessed through the private access mode and the shared access mode in different part of a program without the piece of data being moved in the memory unit (Duluk [0053], [0061], [0071]).
Regarding claim 8, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 6, wherein each of the plurality of columns comprises one PE, the plurality of PEs are identical and form one row of repetitive identical PEs (Isobe Fig 1 & 5:43-50).
Regarding claim 9, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 6, wherein each of the plurality of columns comprises two or more PEs and the plurality of PEs form two or more rows (Isobe Figs 1 & 3-5).
Regarding claim 10, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 9, wherein a first row of PEs are configured to implement a first set of instructions and a second row of PEs are configured to implement a second set of instructions, at least one instruction of the second set of instructions is not in the 4Application No.Attorney Docket No. 6603-0006CON first set of instructions, wherein the of plurality of columns are identical and form repetitive columns (Isobe Figs 1 & 3-5, 5:43-50).
Regarding claim 13, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 7, wherein each of the plurality of memory ports is configured to access the memory unit using a vector address, wherein in the private access mode, one address in the vector address is routed to one memory bank of the memory unit according to a thread index and all private data for one thread are located in a same memory bank (Duluk [0053], [0061], [0071], & [0100], Claim 7, thread indexed sharing).
Regarding claim 14, the combination of Tanaka, Isobe, and Duluk teaches the processor of claim 7, wherein each of the plurality of memory ports is configured to access the memory unit using a vector address, wherein in the shared access mode, one address in the vector address is routed in a defined region across memory banks regardless of the thread index and data shared to all threads are spread in all memory banks (Duluk [0053], [0061], [0071]).
7. Claim 98 is rejected under 35 U.S.C. 103 as being unpatentable over Isobe in view of Eisen (US 2016/0202991, herein Eisen).
Regarding claim 98, Isobe teaches a processor, comprising:
a plurality of processing elements (PEs) (Fig 1, reconfigurable circuits 130) each having a plurality of arithmetic logic units (ALUs) (Isobe Fig 3, 5:5-11, 5:51-62, ALUs); and
a plurality of memory ports (MPs) for the plurality of PEs to access a memory unit for each thread to access a different memory bank in the memory unit (Fig 1, memory 132 & 7:26-35).
Isobe fails to teach wherein the ALUs are configured to execute a same instruction in parallel threads or wherein each of the plurality of MPs comprises an address calculation unit configured to generate respective memory addresses for each thread.
Eisen teaches a processor comprising a plurality of processing elements including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads ([0026], [0029], instruction of same instruction by multiple execution slices as per SIMD execution) and wherein each of a plurality of MPs comprises an address calculation unit configured to generate respective memory addresses for each thread ([0022], [0025], address generation, [0030], address computation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe and Duluk with those of Eisen to utilize SIMD type execution. While Isobe does not explicitly disclose the reconfigurable processor may be used for implementing same instruction type parallel execution, Isobe does contemplate the use of the reconfigurable circuits executing in parallel, and SIMD execution is a routine and conventional aspect of the microprocessor art. As both Isobe and Eisen disclose reconfigurable parallel processor architectures (Isobe Abstract, Eisen [0003], [0009]), this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
8. Claims 11-12 and 99-106 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe and Duluk in view of Eisen.
Regarding claim 11, the combination of Isobe and Duluk teaches the processor of claim 6, wherein each of the plurality of PEs comprises a plurality of arithmetic logic units (ALUs) (Isobe Fig 3, 5:5-11, 5:51-62, ALUs).
Isobe and Duluk fail to teach wherein the ALUs are configured to execute a same instruction in parallel threads.
Eisen teaches a processor comprising a plurality of processing elements including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads ([0026], [0029], instruction of same instruction by multiple execution slices as per SIMD execution).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe and Duluk with those of Eisen to utilize SIMD type execution. While Isobe does not explicitly disclose the reconfigurable processor may be used for implementing same instruction type parallel execution, Isobe does contemplate the use of the reconfigurable circuits executing in parallel, and SIMD execution is a routine and conventional aspect of the microprocessor art. As both Isobe and Eisen disclose reconfigurable parallel processor architectures (Isobe Abstract, Eisen [0003], [0009]), this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 12, the combination of Isobe, Duluk, and Eisen teaches the processor of claim 11, wherein each of the plurality of PEs comprises a plurality of data buffers for the plurality of ALUs and is configured to operate independently (Isobe Figs 1 & 3, 5:43-62).
Regarding claim 99, the combination of Isobe and Eisen teaches the processor of claim 98. Isobe and Eisen fail to teach wherein the address calculation unit has a first input coupled to a base address input that provides a base address common to all threads, a second input coupled to a vector address that provides address offsets for each thread individually, and a third input coupled to a counter that is configured to provide thread indexes ([0084], base address, [0100], SM & warp index,
Duluk teaches wherein the address calculation unit has a first input coupled to a base address input that provides a base address common to all threads, a second input coupled to a vector address that provides address offsets for each thread individually, and a third input coupled to a counter that is configured to provide thread indexes ([0084], base address, [0100], SM & warp index, per-thread addressing).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe and Eisen with those of Duluk to utilize multiple addressing types. While Isobe does not explicitly disclose the means by which addresses are generated, Isobe does disclose the use of addresses transmitted between memory communication hardware and the reconfigurable processing elements. As both Isobe and Duluk disclose reconfigurable parallel processor architectures (Isobe Abstract, Duluk [0103]), this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 100, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 99, wherein one address in the vector address is routed to one memory bank according to a thread index (Duluk [0100], thread indexing).
Regarding claim 101, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 99, wherein the memory unit comprises a plurality of memory caches each associated with a different memory bank (Duluk [0070], memory banks & [0047-0048], caching).
Regarding claim 102, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 101, wherein each of the plurality of memory ports are coupled to the plurality of memory caches (Duluk [0047-0048], caches).
Regarding claim 103, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 101, wherein each memory bank comprises a plurality of memory words and a cache miss in a memory cache causes a word to be fetched from a memory bank associated with the memory cache (Duluk [0060-0061], entries storing 32-bit words & [0088], cache miss fetching).
Regarding claim 104, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 99, wherein each of the plurality of PEs comprises a plurality of data buffers to store data for each thread separately (Isobe Figs 1 & 3, 5:43-62).
Regarding claim 105, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 99, further comprising a sequencer coupled to the plurality of memory ports, wherein each of the plurality of memory ports comprises a configuration buffer to receive one or more configurations from the sequencer, and each memory port is configured to provide a same memory access pattern during one configuration (Isobe Fig 1, control unit 113, 6:53-67 & 5:1-4, configurations).
Regarding claim 106, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 99, wherein consecutive data pieces for one thread are located in one word of a memory bank and continue in a next word of the memory bank (Duluk [0070]).
9. Claims 115 is rejected under 35 U.S.C. 103 as being unpatentable over Isobe, Duluk, and Eisen in view of Kim (US 2014/03171628).
Regarding claim 115, the combination of Isobe, Eisen, and Duluk teaches the processor of claim 98. Isobe, Eisen, and Duluk fail to teach wherein the memory unit is configured to be used as registers to store spilled variables for register spilling.
Kim teaches a processor wherein a memory unit is configured to be used as registers to store spilled variables for register spilling ([0037], [0040], [0043], [0047], register and memory spill instructions to spill register values to memory).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe, Duluk, and Eisen with those of Kim to utilize register spilling. While Isobe does not disclose how register values may be handled by the memory unit, one of ordinary skill in the art would understand that saving or spilling register values for later usage is a routine and conventional aspect of the microprocessor art. As both Isobe and Kim disclose the use of a reconfigurable processor architecture and structures for controlling memory accesses, this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
10. Claims 15-16 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe in view of Tanaka and Ishebabi (US 2011/0231644).
Regarding claim 15, Isobe teaches a method, comprising:
mapping a virtual data path at a processor, wherein the processor comprises various reconfigurable units that include a gasket memory (Fig 1, reconfigurable circuits 130, retiming output buffers, 6:45-52);
delivering configurations to various reconfigurable units of the processor for the various reconfigurable units (reconfigurable circuits 130, retiming output buffers, 6:45-52, control unit 113, 6:53-67 & 5:1-4, configurations); and
operating the various reconfigurable units according to the configurations, including routing data from one physical data path to the gasket memory to be used in a future physical data path as input (Fig 1, input data dividing unit & retiming selection buffers 190, 6:30-33).
Isobe and Tanaka fail to teach the instructions being part of an execution kernel or chopping the virtual data path into one or more physical data paths.
Tanaka teaches a method comprising mapping instructions into a virtual data path at a processor, wherein the instruction include a sequence of instructions to be executed by the processor, and the processor comprises various reconfigurable units, and forming the one or more data paths using the various reconfigurable units by delivering configurations to the various reconfigurable units to execute the sequence of instructions (Figs 2, 5, [0046-0048], [0052-0056], distributing configurations via a buffer and manager to multiple reconfigurable processors including a reconfigurable array, reconfigurable processors include a local memory for instructions to be executed, reconfiguration controlled by subprocessor SPU).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tanaka and Isobe to utilize the reconfigurable architecture for delivering and executing instructions in a datapath. While Isobe does not explicitly state that the processing operations to be performed by the reconfigurable processors may include instructions to be mapped and executed, one of ordinary skill in the art would understand that the use of instructions to control the execution of processing elements at any scale is a routine and conventional aspect of the microprocessor art. Therefore, utilizing the reconfigurable hardware of Isobe for transferring and executing instructions to perform the processor operations would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Ishebabi teaches a method comprising mapping an execution kernel into a virtual data path at a processor ([0030], mapping kernel onto execution constructs of an FPGA) and chopping the virtual data path into one or more physical data paths, ([0030], mapping kernel to physical hardware & [0033], [0044], construct new data paths according to FPGA configuration).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe and Tanaka with those of Ishebabi in order to utilize data path mapping. While Isobe does not explicitly disclose the instructions being executed by the processor being embodied as an execution kernel or the reconfigurable hardware being embodied as one or more datapaths, one of ordinary skill in the art would understand these constructs are routine and conventional aspects of the microprocessor art. As both Isobe and Ishebabi disclose the use of reconfigurable logic for executing programs, this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 16, the combination of Isobe, Tanaka, and Ishebabi teach the method of claim 15, wherein the various reconfigurable units further comprise a plurality of processing elements, a plurality of switch boxes each associated with a separate processing element, a plurality of memory ports that provide access to a memory unit for the plurality of processing elements, and a plurality of inter-column switch boxes, where each of the various reconfigurable units are reconfigured by applying a next configuration independently from other reconfigurable units (Isobe Fig 1, memory 132 & 7:26-35, control unit 113, 6:53-67 & 5:1-4, configurations & processed data selection units 111 & 112).
Regarding claim 22, the combination of Isobe, Tanaka, and Ishebabi teach the method of claim 16, wherein the plurality of PEs form a PE array and the execution kernel is mapped into one or more physical data paths on the processor based on a size of the PE array, connections between the plurality of PEs, and memory access capability (Ishebabi [0033], [0044], arranging datapaths according to hardware requirements).
Regarding claim 23, the combination of Isobe, Tanaka, and Ishebabi teach the method of claim 15, wherein the various reconfigurable units form multiple repetitive columns, and each of the one or more physical data paths is fitted into the multiple repetitive columns, and data flows between the repetitive columns are in one direction (Isobe Figs 1 & 3-5, 5:43-50).
11. Claims 17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe, Tanaka, and Ishebabi, and further in view of Eisen.
Regarding claim 17, the combination of Isobe, Tanaka, and Ishebabi teach the method of claim 16. Isobe, Tanaka, and Ishebabi fail to teach wherein each of the plurality of PEs comprises a plurality of arithmetic logic units (ALUs) that are configured to execute same instruction in parallel threads.
Eisen teaches a processor comprising a plurality of processing elements including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads ([0026], [0029], instruction of same instruction by multiple execution slices as per SIMD execution).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe, Tanaka, and Ishebabi with those of Eisen to utilize SIMD type execution. While Isobe does not explicitly disclose the reconfigurable processor may be used for implementing same instruction type parallel execution, Isobe does contemplate the use of the reconfigurable circuits executing in parallel, and SIMD execution is a routine and conventional aspect of the microprocessor art. As both Isobe and Eisen disclose reconfigurable parallel processor architectures (Isobe Abstract, Eisen [0003], [0009]), this combination would merely entail combining known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 21, the combination of Isobe, Ishebabi, and Eisen teach the method of claim 17, wherein each of the plurality of PEs comprises a plurality of data buffers for the plurality of ALUs and is configured to operate independently during one physical data path (Isobe Fig 1, reconfigurable circuits 130 & configuration buffers 121, 5:51-52, ALU-type circuits & 7:22-25).
12. Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Isobe, Tanaka, Ishebabi, and Eisen, and further in view of Duluk.
Regarding claim 18, the combination of Isobe, Tanaka, Ishebabi and Eisen teaches the method of claim 17. Isobe, Tanaka, Ishebabi and Eisen fail to teach wherein each of the plurality of memory ports is configured to operate in a private access mode or a shared access mode during one configuration.
Duluk teaches a processor wherein memory ports of a reconfigurable processing element are configured to operate in a private access mode or a shared access mode during one MP configuration ([0103], reconfiguring PPUs & [0053], [0061], [0071], configuring memory to be shared between thread arrays).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Isobe, Tanaka, Ishebabi, and Eisen with those of Duluk to utilize shared memory access in the parallel processor. While Isobe only discloses the exemplary reconfigurable parallel processor as each processing element utilizing its own distinct memory, Isobe does disclose the communication unit retrieving information from outside the processor to configure the processing elements (Isobe 7:8-21). Therefore, utilizing an external shared memory when appropriate for programs which share a thread array indicator, as taught by Duluk, would allow for the processor to have a distinct shared memory space rather than continually transferring the necessary data between local memories of each configurable element. As threaded execution is a routine and conventional aspect of the microprocessor art, this would merely entail a combination of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 19, the combination of Isobe, Tanaka, Ishebabi, Eisen, and Duluk teaches the method of claim 18, further comprising accessing a piece of data stored in the memory unit through the private access mode and the shared access mode in different physical data paths without the piece of data being moved in the memory unit (Duluk [0053], [0061], [0071]).
Allowable Subject Matter
13. Claims 20 and 109-113 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183