Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 and 10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (CN 112802855, machine-translation provided).
Regarding Claim 1
FIG. 1 of Hu discloses a microelectronic device, comprising: a memory cell comprising: a first transistor structure (20); a second transistor structure (20) vertically overlying the first transistor structure; a storage device (10) vertically overlying the second transistor structure; a first conductive contact structure (31) contacting the first transistor structure, the second transistor structure, and a first electrode (33) of the storage device, each of the first transistor structure and the second transistor structure in electrical communication with the first electrode through the first conductive contact structure; and a second conductive contact structure (32) configured to be in electrical communication with the first transistor structure and the second transistor structure.
Regarding Claim 10
FIG. 1 of Hu discloses a memory device, comprising: an array of memory cells, each memory cell of the array of memory cells comprising: a first transistor (lower 20) vertically spaced from a second transistor (upper 20) vertically overlying the first transistor; a capacitor (10) vertically overlying the first transistor and the second transistor, the capacitor comprising: a first electrode material; a second electrode material; and a dielectric material between the first electrode material and the second electrode material, the first electrode material, the second electrode material, and the dielectric material individually comprising vertical levels spaced from one another by levels of insulative material; and a first conductive contact structure (31+33) in contact with the first transistor, the second transistor, and the first electrode material, the first conductive contact structure vertically extending through the second transistor and at least partially through the first transistor.
Claims 1 and 10 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (CN 110192269, machine-translation provided).
Regarding Claim 1
FIG. 13 of Liu discloses a microelectronic device, comprising: a memory cell comprising: a first transistor structure (101); a second transistor structure (103) vertically overlying the first transistor structure; a storage device (740) vertically overlying the second transistor structure; a first conductive contact structure (944) contacting the first transistor structure, the second transistor structure, and a first electrode (918) of the storage device, each of the first transistor structure and the second transistor structure in electrical communication with the first electrode through the first conductive contact structure; and a second conductive contact structure (844) configured to be in electrical communication with the first transistor structure and the second transistor structure.
Regarding Claim 10
FIG. 13 of Liu discloses a memory device, comprising: an array of memory cells, each memory cell of the array of memory cells comprising: a first transistor (101) vertically spaced from a second transistor (103) vertically overlying the first transistor; a capacitor (740) vertically overlying the first transistor and the second transistor, the capacitor comprising: a first electrode material; a second electrode material; and a dielectric material between the first electrode material and the second electrode material, the first electrode material, the second electrode material, and the dielectric material individually comprising vertical levels spaced from one another by levels of insulative material; and a first conductive contact structure (944) in contact with the first transistor, the second transistor, and the first electrode material, the first conductive contact structure vertically extending through the second transistor and at least partially through the first transistor.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 6, 7, 10 and 14 rejected under 35 U.S.C. 103 as being unpatentable over Park (U.S. Patent Pub. No. 2009/0168482) of record, in view of Toda (U.S. Patent Pub. No. 2007/0285965) of record.
Regarding Claim 1
FIG. 1 of Park discloses a microelectronic device, comprising: a first transistor structure (110); a second transistor structure (120) vertically overlying the first transistor structure; a storage device (capacitor in 130-140); a first conductive contact structure (vertical via including BL, FIG. 3) contacting the first transistor structure and the second transistor structure, each of the first transistor structure and the second transistor structure in electrical communication with the first conductive contact structure; and a second conductive contact structure (rightmost via) configured to be in electrical communication with the first transistor structure and the second transistor structure.
Park is silent with respect to “a storage device vertically overlying the second transistor structure” and “each of the first transistor structure and the second transistor structure in electrical communication with the first electrode through the first conductive contact structure”.
FIG. 7 of Toda discloses a similar microelectronic device, comprising a storage device (MC) vertically overlying the second transistor structure and a first conductive contact structure (101+Bl0) contacting a first electrode of the storage device.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Toda. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of performing high-speed data input/output ([0011] of Toda).
Regarding Claim 2
FIG. 3 of Park discloses a conductive line (104) coupled to the second conductive contact structure.
Regarding Claim 4
FIG. 3 of Park discloses the conductive line is vertically between the first transistor structure and the storage device.
Regarding Claim 6
FIG. 1 of Park discloses a vertical height of the storage device (130-140) is greater than a vertical height of the first transistor structure (110) and the second transistor structure (120).
Regarding Claim 7
FIG. 3 of Park discloses the second transistor structure (142) is located within horizontal boundaries of the first transistor structure (110).
Regarding Claim 10
FIG. 3 of Park discloses a memory device, comprising: an array of memory cells [0006], each memory cell of the array of memory cells comprising: a first transistor (111) vertically spaced from a second transistor (142) vertically overlying the first transistor; a capacitor (Capacitor) comprising: a first electrode material; a second electrode material; and a dielectric material between the first electrode material and the second electrode material, wherein the first electrode material, the second electrode material, and the dielectric material individually comprise vertical levels spaced from one another by levels of insulative material; and a first conductive contact structure in contact with the first transistor and the second transistor, the first conductive contact structure vertically extending through the second transistor and at least partially through the first transistor.
Park is silent with respect to “a capacitor vertically overlying the first transistor and the second transistor” a first conductive contact structure contacting “the first electrode”.
FIG. 7 of Toda discloses a similar microelectronic device, comprising a storage device (MC) vertically overlying the second transistor structure and a first conductive contact structure (101+Bl0) contacting a first electrode of the storage device.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Toda. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of performing high-speed data input/output ([0011] of Toda).
Regarding Claim 14
FIG. 3 of Park discloses a conductive line configured to be in electrical communication with the first transistor (111) and the second transistor (142), the conductive line vertically spaced from the capacitor by the first transistor and the second transistor.
Claims 1, 8, 10, 22 and 23 rejected under 35 U.S.C. 103 as being unpatentable over Yang (U.S. Patent Pub. No. 2023/0005543) of record, in view of Shuto (U.S. Patent Pub. No. 2011/0018043).
Regarding Claim 1
FIG. 23A of Yang discloses a microelectronic device, comprising: a first transistor structure (104); a second transistor structure (102 below 106) vertically overlying the first transistor structure; a storage device (2327) vertically overlying the second transistor structure; a first conductive contact structure (rightmost vertical via including an interconnect layer 2328) contacting the first transistor structure, the second transistor structure, and the storage device, each of the first transistor structure and the second transistor structure in electrical communication with the first conductive contact structure; and a second conductive contact structure (2330) configured to be in electrical communication with the first transistor structure and the second transistor structure.
Yang is silent with respect to a first conductive contact structure contacting “a first electrode of the storage device” and “in electrical communication with the first electrode”.
FIG. 3 of Shuto discloses a similar microelectronic device, comprising a first conductive contact structure (CP+M0) contacting a first electrode (LE) of the storage device and in electrical communication with the first electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Shuto. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of reducing chip size ([0005] of Shuto).
Regarding Claim 8
FIG. 23A of Yang discloses the storage device comprises: first vertically spaced portions of a first electrode material; and vertically spaced portions of a second electrode material.
Regarding Claim 10
FIG. 23A of Yang discloses a memory device, comprising: an array of memory cells [0005], each memory cell of the array of memory cells comprising: a first transistor (104) vertically spaced from a second transistor (102 below 106) vertically overlying the first transistor; a capacitor vertically overlying the first transistor and the second transistor [0069]; and a first conductive contact structure (rightmost vertical via) in contact with the first transistor, the second transistor, the first conductive contact structure vertically extending through the second transistor and at least partially through the first transistor.
Yang is silent with respect to “the capacitor comprising: a first electrode material; a second electrode material; and a dielectric material between the first electrode material and the second electrode material, wherein the first electrode material, the second electrode material, and the dielectric material individually comprising vertical levels spaced from one another by levels of insulative material” and a first conductive contact in contact with “the first electrode”.
FIG. 3 of Shuto discloses a similar microelectronic device, comprising a capacitor vertically overlying the second transistor and a first conductive contact structure (CP+M0), wherein the capacitor comprising: a first electrode material (LE); a second electrode material (UE); and a dielectric material (FE) between the first electrode material and the second electrode material, wherein the first electrode material, the second electrode material, and the dielectric material individually comprising vertical levels spaced from one another by levels of insulative material, and the first conductive contact in contact with the first electrode of the storage device and in electrical communication with the first electrode.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Shuto. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of reducing chip size ([0005] of Shuto).
Regarding Claim 22
FIG. 23A of Yang discloses the storage device comprises at least five vertical levels of each of the first electrode material and the second electrode material.
Regarding Claim 23
FIG. 23A of Yang discloses the first transistor (104) and the second transistor (2314) are individually located within horizontal boundaries of one another.
Claims 16, 19 and 24 rejected under 35 U.S.C. 103 as being unpatentable over Yang (U.S. Patent Pub. No. 2023/0005543) of record, in view of, in view of Shao (CN 115483213, machine-translation provided).
Regarding Claim 16
FIG. 36 of Yang discloses a electronic system, comprising: an input device; an output device; a processor device (3608) operably coupled to the input device [0060] and the output device [0350]; and a memory device operably coupled to the processor device and comprising at least one microelectronic device (FIG. 23A), the at least one microelectronic device comprising: a vertical stack of transistors comprising vertical pairs of transistors, the transistors of each of the vertical pairs of transistors vertically spaced from one another; and a stack structure comprising capacitors (formed by horizontal lines within 2327) vertically overlying the vertical stack of transistors [0069]; and conductive contact structures individually in contact with both of the transistors of a respective vertical pair of the transistors.
Yang is silent with respect to “each of the capacitors configured to be in electrical communication with a respective vertical pair of the transistors to form a memory cell, the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors” and conductive contact structures in contact with an electrode of a respective one of the capacitors.
FIG. 3 of Shuto discloses a similar microelectronic device, wherein each of the capacitors configured to be in electrical communication with a respective vertical pair of the transistors to form a memory cell; and conductive contact structures individually in contact with the transistors and with an electrode of a respective one of the capacitors.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Shuto. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of reducing chip size ([0005] of Shuto).
Yang as modified by Lee is silent with respect to “the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors”.
FIG. 6 of Shao discloses a similar microelectronic device, wherein each of the capacitors (CAP) configured to be in electrical communication with a respective vertical pair of the transistors to form a memory cell (although FIG. 4 of Lee does not show CAP1 vertically overlying the vertical stack of transistors, one of ordinary skill in the art would understand CAP1 can be directly stacked on CAP2) the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors. Moreover, said thicknesses are related to the device size and desired capacitances. Therefore, said thicknesses is considered to be a result effective variable. The claim to specific thickness therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Shao. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of improving the integrated density of the semiconductor structure and reducing the difficulty of the capacitor lead (Abstract of Shao).
Regarding Claim 19
FIG. 6 of Shao discloses additional conductive contact structures (201) in contact with a conductive line vertically underlying the vertical stack of transistors and configured to electrically connect the transistors to the conductive line.
Regarding Claim 24
FIG. 23A of Yang discloses a conductive line (2316) vertically between the vertical stack of transistors and the stack structure and configured to be in electrical communication with the transistors of the vertical pairs of transistors.
Claims 3 and 8 rejected under 35 U.S.C. 103 as being unpatentable over Park and Toda, in view of Wang (U.S. Patent Pub. No. 2008/0057641) of record.
Regarding Claim 3
Park as modified by Toda discloses Claim 2.
Park as modified by Toda is silent with respect to “the conductive line is vertically separated from the storage device by the first transistor structure and the second transistor structure”.
FIG. 1 of Wang discloses a similar microelectronic device, wherein the conductive line (75) is vertically separated from the storage device (35) by the first transistor structure and the second transistor structure.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Wang. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of storing a large amount of data ([0005] of Wang).
Regarding Claim 8
FIG. 1 of Wang discloses the storage device comprises: first vertically spaced portions of a first electrode material; and vertically spaced portions of a second electrode material.
Claims 5 and 21 rejected under 35 U.S.C. 103 as being unpatentable over Yang and Shao, in view of Wu (U.S. Patent Pub. No. 2021/0399052) of record.
Regarding Claim 5
Yang as modified by Shao discloses Claim 1.
Yang as modified by Shao is silent with respect to “the first conductive contact structure vertically extends through the first transistor structure and the second transistor structure”.
FIG. 20 of Wu discloses a similar microelectronic device, wherein the first conductive contact structure (114-126) vertically extends through the first transistor structure and the second transistor structure.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Wu. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of increasing production efficiency and lowering associated costs ([0002] of Wu).
Regarding Claim 21
FIG. 23 of Yang discloses a portion of the first conductive contact structure within the first transistor structure is substantially surrounded by a material (2302) of the first transistor structure.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Yang and Shao, in view of Lee (U.S. Patent Pub. No. 2008/0296554) of record.
Regarding Claim 9
Yang as modified by Shao discloses Claim 1, wherein the first conductive contact structure is horizontally offset from the second conductive contact structure in a first horizontal direction”.
Yang as modified by Shao is silent with respect to “the first conductive contact structure is horizontally offset from the second conductive contact structure in a first horizontal direction and a second horizontal direction”.
FIG. 5A of Lee discloses a similar microelectronic device, wherein the first conductive contact structure is horizontally offset from the second conductive contact structure (130) in a first horizontal direction and a second horizontal direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Yang, as taught by Lee. The ordinary artisan would have been motivated to modify Yang in the above manner for purpose of improving integration ([0011] of Lee).
Claims 10 and 11 rejected under 35 U.S.C. 103 as being unpatentable over Park, in view of Durcan (U.S. Patent No. 6,159,818) of record.
Regarding Claim 10
FIG. 3 of Park discloses a memory device, comprising: an array of memory cells [0006], each memory cell of the array of memory cells comprising: a first transistor (111) vertically spaced from a second transistor (142) vertically overlying the first transistor; a capacitor (Capacitor) comprising: a first electrode material; a second electrode material; and a dielectric material between the first electrode material and the second electrode material, wherein the first electrode material, the second electrode material, and the dielectric material individually comprise vertical levels spaced from one another by levels of insulative material; and a first conductive contact structure in contact with the first transistor and the second transistor, the first conductive contact structure vertically extending through the second transistor and at least partially through the first transistor.
Park is silent with respect to “a capacitor vertically overlying the first transistor and the second transistor” a first conductive contact structure contacting “the first electrode”.
FIG. 12 of Durcan discloses a similar microelectronic device, comprising a capacitor (8) vertically overlying the second transistor (5), the capacitor comprising: a first electrode material (20); a second electrode material (24); and a dielectric material (23) between the first electrode material and the second electrode material, wherein the first electrode material, the second electrode material, and the dielectric material individually comprise vertical levels spaced from one another by levels of insulative material; and a conductive contact structure (15) in contact with the first transistor and the first electrode
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Durcan. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of dense memory arrays (Col. 1, Lines 5-8 of Durcan).
Regarding Claim 11
FIG. 3 of Park discloses second conductive contact structures (via connecting 104), each of the second conductive contact structures vertically extending adjacent to the first transistor and the second transistor of a memory cell and configured to be in electrical communication with the first transistor and the second transistor.
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Park and Lee839, in view of Liaw (U.S. Patent Pub. No. 2020/0135740) of record.
Regarding Claim 15
Park as modified by Lee839 discloses Claim 10.
Park as modified by Lee839 is silent with respect to “the first transistor and the second transistor individually comprise gate-all-around (GAA) transistors”.
FIG. 2 of Liaw discloses a similar microelectronic device, wherein the first transistor and the second transistor individually comprise gate-all-around (GAA) transistors [0052].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Liaw. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of high performance and low leakage applications ([0003] of of Liaw).
Claims 16 and 18 rejected under 35 U.S.C. 103 as being unpatentable over Park, in view of Toda, in view of Fulford (U.S. Patent Pub. No. 2023/0200052) of record.
Regarding Claim 16
FIG. 11 of Park discloses an electronic system, comprising: an input device; an output device [0025]; a processor device (12) operably coupled to the input device and the output device; and a memory device (18) operably coupled to the processor device and comprising at least one microelectronic device, the at least one microelectronic device comprising: a vertical stack of transistors comprising vertical pairs of transistors (111 and 142, FIG. 3), the transistors of each of the vertical pairs of transistors vertically spaced from one another; and conductive contact structures individually in contact with both of the transistors of a respective vertical pair of the transistors.
Park is silent with respect to “a stack structure comprising capacitors vertically overlying the vertical stack of transistors, each of the capacitors configured to be in electrical communication with a respective vertical pair of the transistors to form a memory cell, the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors” and conductive contact structures individually in contact with an electrode of a respective one of the capacitors.
FIG. 7 of Toda discloses a similar microelectronic device, comprising a stack structure comprising capacitors (MC) vertically overlying the vertical stack of transistors (although FIG. 7 of Toda does not show transistors 201 and 202 are vertically stacked, one of ordinary skill in the art would understand the transistors can be vertically stacked, as shown in FIG. 4 of Toda), each of the capacitors configured to be in electrical communication with a respective vertical pair of the transistors to form a memory cell, the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors; and conductive contact structures (101+BL0) individually in contact with the transistors and with an electrode of a respective one of the capacitors.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Toda. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of storing a large amount of data ([0005] of Toda).
Park as modified by Toda is silent with respect to “the stack structure having a greater thickness in a vertical direction than the vertical stack of transistors”.
FIG. 7 of Fulford discloses a similar microelectronic device, wherein the stack structure (270) having a greater thickness in a vertical direction than the vertical stack of transistors (260). Moreover, said thicknesses are related to the device size and desired capacitances. Therefore, said thicknesses is considered to be a result effective variable. The claim to specific thickness therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Park, as taught by Fulford. The ordinary artisan would have been motivated to modify Park in the above manner for purpose of forming higher density semiconductor devices ([0004] of Fulford).
Regarding Claim 18
FIG. 7 of Toda discloses a bottom electrode of each capacitor of the capacitors is in electrical communication with the vertical pair of the transistors vertically underlying the capacitor.
Pertinent Art
US 20030129829, 20210398897, 20230225131, 20080191312, 20200328176, CN 112614831 and 116391452.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 10 and 16 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897
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