DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Response to Amendment
Applicant`s remarks filed 08/25/2026 regarding the claim 1, claim objection submitted in the non-final office action dated 06/012026 is withdrawn due to the amendments made to Claim 1.
Response to Arguments
Applicant’s arguments see remarks, filed 08/25/2026, with respect to claims 1-10, have been fully considered and are persuasive.
The applicant argues on page 9, “that the claimed invention of the present application and the subject matter disclosed in Hong (U.S. Patent Application Publication No. 2024/0055307) relied upon in the Office Action were, not later than the effective filing date of the claimed invention, owned by Samsung Electronics Co., Ltd. or subject to an obligation of assignment to Samsung Electronics Co., Ltd. Accordingly, pursuant to 35 U.S.C. § 102(b)(2)(C), the subject matter disclosed in Hong and relied upon in the Office Action is excepted as prior art under 35 U.S.C. § 102(a)(2) and may not be relied upon in a rejection under 35 U.S.C. § 103. Additionally, because Hong's publication occurred after the May 12, 2023 effective filing date of claims 1-10 and 20, Hong does not qualify as prior art under 35 U.S.C. § 102(a)(1) with respect to those claims. Applicant therefore respectfully requests withdrawal of the § 103 rejections of claims 1-10 and 20 relying upon Hong.”
In response, the office do find this argument to be persuasive. After a careful search and consideration claims 1-10 are indicated below in the office document as being allowable.
Applicant’s arguments see remarks, filed 08/25/2026, with respect to claims 11-20, have been fully considered but are not persuasive.
The office would like to bring to applicant`s attention that amended claims 13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph.
The applicant argues on page 9-10, “claim 11 to include features not disclosed, taught, or suggested by the cited references, alone or in combination. Applicant respectfully asserts that at least the limitation that "the adhesive film is interposed between the second semiconductor chip and the upper surface of the first semiconductor chip" is not disclosed, taught, or suggested by the cited references.”
In response, the office does not find this argument to be persuasive. Based on the breadth of the claim language the prior art OH et al. (US 20190295986 A1), explicitly teaches a semiconductor package (Fig. 6, #4000 called a semiconductor package. Paragraph [0052]), comprising:
a package substrate (Fig. 6, #100 called a package substrate. Paragraph [0024]) having a receiving groove that has a predetermined depth from an upper surface of the package substrate (Fig. 6, illustrates a receiving groove wherein the first pads #101 is in an opening on the surface of the package substrate #100. Paragraph [0025]);
a first semiconductor chip (Fig. 6, #300a-b called a second and third semiconductor chips. Paragraph [0025]) disposed in the receiving groove of the package substrate (Fig. 6, illustrates the receiving groove wherein the first pads #101 is in an opening on the surface of the package substrate #100 houses the first semiconductor chip ##300a-b via the connecting terminals #240. Paragraph [0036 and 0037]);
a second semiconductor chip (Fig. 6, #600 called a fourth semiconductor chip. Paragraph [0043]) attached to an upper surface of the first semiconductor chip (Fig. 6, #300a-b called a second and third semiconductor chips. Paragraph [0025]) by an adhesive film to expose a portion of the upper surface of the first semiconductor chip (Fig. 6, illustrates the second semiconductor chip #600 is located on a part of the upper surface of the first semiconductor chip #300a-b via an adhesive film #340. Paragraph [0046]-OH discloses an adhesive layer 340 may be interposed between a first semiconductor chip 200 and each of second and third semiconductor chips 300a and 300b.);
an underfill member filling (Fig. 6, #101, #240 and #203 called first pads, terminals, and first chip pads respectively. Paragraph [0036]) the receiving groove of the package substrate (Fig 6. Paragraph [0036]-OH discloses the package substrate 100 and the first semiconductor chip 200 may be provided therebetween with terminals (or, connection members) 240. For example, the terminals 240 may be disposed between the first chip pads 203 and the first pads 101. The terminals 240 may be in contact with the first chip pads 203.),
wherein the underfill member includes a first cover portion (Fig. 6, #101 called first pads. Paragraph [0036]), a second cover portion (Fig. 6, #240 called terminals. Paragraph [0036]), and a third cover portion (Fig. 6, 203 called first chip pads. Paragraph [0036]), wherein the first cover portion fills a gap between the first semiconductor chip and a bottom surface of the receiving groove (Fig. 6, illustrates the first cover portion fills #101 fills a gap between the first semiconductor chip #300a-b and the bottom of the receiving groove. Paragraph [0036]-OH discloses the terminals 240 may be disposed between the first chip pads 203 and the first pads 101.), wherein the adhesive film is interposed between the second semiconductor chip and the upper surface of the first semiconductor chip (Fig. 6, illustrates the second semiconductor chip #600 is located on a part of the upper surface of the first semiconductor chip #300a-b via an adhesive film #340. Paragraph [0046]-OH discloses an adhesive layer 340 may be interposed between a first semiconductor chip 200 and each of second and third semiconductor chips 300a and 300b.).
OH fail to explicitly teaches the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove;
and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
However, KIM explicitly teaches the second cover portion (Fig. 18, #140 called an insulating layer. Paragraph [0067 and 0098]) covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip (Fig. 18, illustrates second cover portion covers #140 is over the upper surface of the first semiconductor chip #120 that is exposed by the second semiconductor chip #130a. Paragraph [0096]), and the third cover portion covers (Fig. 18, #135a-b called an attachment member. Paragraph [0100]) gap between the first semiconductor chip and a sidewall of the receiving groove (Fig. 18, illustrates the third cover portion covers #135a-b gap between the first semiconductor chip and a sidewall of the receiving groove under the #130b. Paragraph [0096]);
and a molding member (Fig. 18, #160 called a molding member. Paragraph [0079]) covering the first semiconductor chip (Fig. 18, #120 first semiconductor chip. Paragraph [0097]), the second semiconductor chip (Fig. 18, #120 first semiconductor chip. Paragraph [0097]), and the underfill member (Fig. 2 and 18, #125 called a underfill resin. Paragraph [0027]) and disposed on the package substrate (Fig. 18, #110 called a package substrate. Paragraph [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH of having a semiconductor package, comprising: a package substrate having a receiving groove that has a predetermined depth from on an upper surface of the package substrate; a first semiconductor chip disposed in the receiving groove of the package substrate; a second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive film to expose a portion of the upper surface of the first semiconductor chip, with the teachings of KIM of having wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
Wherein having OH’s a semiconductor package structure, wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, heat dissipation and minimum feature size, since both OH and KIM are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while KIM 1’s semiconductor structure system provide a semiconductor package having enhance reliability by improving heat dissipation performance and suppressing defects such as warpage, cracking, or the like. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and KIM et al. (US 20210057380 A1), Paragraphs [0105].
The applicant further argues on page 10, “that the cited combination does not disclose or suggest, an adhesive film interposed between the second semiconductor chip and the upper surface of the first semiconductor chip, as now recited in claim 11.”
In response, the office does not find this argument to be persuasive based on the same reasons set forth above and the rejection below. The office respectfully encourages applicant to amendment the claims to overcome the prior arts of record.
The applicant further argues on page 10, “that a prima facie case of obviousness against independent claim 11 cannot stand, as a proper obviousness rejection requires that the prior art disclose or suggest all claim limitations and provide a reason to combine the teachings of the references.”
In response, the office does not find this argument to be persuasive. The office would like to respectfully bring to the applicant`s attention that there is teaching, suggestion, or motivation to combine the references, the office recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the office have clearly describe that it would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of OH of having a semiconductor package, comprising: a package substrate having a receiving groove that has a predetermined depth from on an upper surface of the package substrate; a first semiconductor chip disposed in the receiving groove of the package substrate; a second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive film to expose a portion of the upper surface of the first semiconductor chip, with the teachings of KIM of having wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
Wherein having OH’s a semiconductor package structure, wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, heat dissipation and minimum feature size, since both OH and KIM are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while KIM’s semiconductor structure system provide a semiconductor package having enhance reliability by improving heat dissipation performance and suppressing defects such as warpage, cracking, or the like. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and KIM et al. (US 20210057380 A1), Paragraphs [0105].
The applicant further argues on page 10, “The additional references applied against the dependent claims do not remedy at least the foregoing deficiency of independent claim 11 from which they depend. Accordingly, the dependent claims are patentable for at least the same reasons as amended independent claim 11 from which they depend.”
In response, the office does not find this argument to be persuasive as disclosed above and below. The office respectfully encourages applicant to amendment the claims to overcome the prior arts of record.
The applicant further argues on page 10, “that the rejections of claims 11-19 are overcome and
respectfully requests that the rejections of claims 11-19 under 35 U.S.C. § 103 be withdrawn.”
In response, the office does not find this argument to be persuasive base on the same reasons set forth above and in the rejection below.
The applicant further argues on page 10, “that this application should be allowed and the case passed to issue.”
In response, the office does not find this argument to be persuasive based on the same reasons set forth above and in the rejection below. The office respectfully encourages applicant to amendment the claims to overcome the prior arts of record and the rejection under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for wherein a thickness of the second cover portion of the underfill member is within a range of about 5 μm to about 30 μm as described in paragraph [0006] in the specification, does not reasonably provide enablement for explicitly disclosing “wherein a thickness of the second cover portion of the underfill member is within a range of 5 μm to 30 μm, inclusive.”
The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to use the invention commensurate in scope with these claims. The claimed subject matter does not teach wherein a thickness of the second cover portion of the underfill member is within a range of 5 μm to 30 μm, inclusive.
The office respectfully requests the Applicant to amend in order to overcome the rejected under 35 U.S.C. 112(a.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM.
Regarding claim 11, OH teaches a semiconductor package (Fig. 6, #4000 called a semiconductor package. Paragraph [0052]), comprising:
a package substrate (Fig. 6, #100 called a package substrate. Paragraph [0024]) having a receiving groove that has a predetermined depth from an upper surface of the package substrate (Fig. 6, illustrates a receiving groove wherein the first pads #101 is in an opening on the surface of the package substrate #100. Paragraph [0025]);
a first semiconductor chip (Fig. 6, #300a-b called a second and third semiconductor chips. Paragraph [0025]) disposed in the receiving groove of the package substrate (Fig. 6, illustrates the receiving groove wherein the first pads #101 is in an opening on the surface of the package substrate #100 houses the first semiconductor chip ##300a-b via the connecting terminals #240. Paragraph [0036 and 0037]);
a second semiconductor chip (Fig. 6, #600 called a fourth semiconductor chip. Paragraph [0043]) attached to an upper surface of the first semiconductor chip (Fig. 6, #300a-b called a second and third semiconductor chips. Paragraph [0025]) by an adhesive film to expose a portion of the upper surface of the first semiconductor chip (Fig. 6, illustrates the second semiconductor chip #600 is located on a part of the upper surface of the first semiconductor chip #300a-b via an adhesive film #340. Paragraph [0046]-OH discloses an adhesive layer 340 may be interposed between a first semiconductor chip 200 and each of second and third semiconductor chips 300a and 300b.);
an underfill member filling (Fig. 6, #101, #240 and #203 called first pads, terminals, and first chip pads respectively. Paragraph [0036]) the receiving groove of the package substrate (Fig 6. Paragraph [0036]-OH discloses the package substrate 100 and the first semiconductor chip 200 may be provided therebetween with terminals (or, connection members) 240. For example, the terminals 240 may be disposed between the first chip pads 203 and the first pads 101. The terminals 240 may be in contact with the first chip pads 203.),
wherein the underfill member includes a first cover portion (Fig. 6, #101 called first pads. Paragraph [0036]), a second cover portion (Fig. 6, #240 called terminals. Paragraph [0036]), and a third cover portion (Fig. 6, 203 called first chip pads. Paragraph [0036]), wherein the first cover portion fills a gap between the first semiconductor chip and a bottom surface of the receiving groove (Fig. 6, illustrates the first cover portion fills #101 fills a gap between the first semiconductor chip #300a-b and the bottom of the receiving groove. Paragraph [0036]-OH discloses the terminals 240 may be disposed between the first chip pads 203 and the first pads 101.), wherein the adhesive film is interposed between the second semiconductor chip and the upper surface of the first semiconductor chip (Fig. 6, illustrates the second semiconductor chip #600 is located on a part of the upper surface of the first semiconductor chip #300a-b via an adhesive film #340. Paragraph [0046]-OH discloses an adhesive layer 340 may be interposed between a first semiconductor chip 200 and each of second and third semiconductor chips 300a and 300b.).
OH fail to explicitly teaches the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove;
and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
However, KIM explicitly teaches the second cover portion (Fig. 18, #140 called an insulating layer. Paragraph [0067 and 0098]) covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip (Fig. 18, illustrates second cover portion covers #140 is over the upper surface of the first semiconductor chip #120 that is exposed by the second semiconductor chip #130a. Paragraph [0096]), and the third cover portion covers (Fig. 18, #135a-b called an attachment member. Paragraph [0100]) gap between the first semiconductor chip and a sidewall of the receiving groove (Fig. 18, illustrates the third cover portion covers #135a-b gap between the first semiconductor chip and a sidewall of the receiving groove under the #130b. Paragraph [0096]);
and a molding member (Fig. 18, #160 called a molding member. Paragraph [0079]) covering the first semiconductor chip (Fig. 18, #120 first semiconductor chip. Paragraph [0097]), the second semiconductor chip (Fig. 18, #120 first semiconductor chip. Paragraph [0097]), and the underfill member (Fig. 2 and 18, #125 called a underfill resin. Paragraph [0027]) and disposed on the package substrate (Fig. 18, #110 called a package substrate. Paragraph [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH of having a semiconductor package, comprising: a package substrate having a receiving groove that has a predetermined depth from on an upper surface of the package substrate; a first semiconductor chip disposed in the receiving groove of the package substrate; a second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive film to expose a portion of the upper surface of the first semiconductor chip, with the teachings of KIM of having wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
Wherein having OH’s a semiconductor package structure, wherein the second cover portion covers the portion of the upper surface of the first semiconductor chip that is exposed by the second semiconductor chip, and the third cover portion covers a gap between the first semiconductor chip and a sidewall of the receiving groove; and a molding member covering the first semiconductor chip, the second semiconductor chip, and the underfill member and disposed on the package substrate.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, heat dissipation and minimum feature size, since both OH and KIM are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while KIM’s semiconductor structure system provide a semiconductor package having enhance reliability by improving heat dissipation performance and suppressing defects such as warpage, cracking, or the like. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and KIM et al. (US 20210057380 A1), Paragraphs [0105].
Regarding claim 15, OH in view of KIM teaches the semiconductor package of claim 11, OH further teaches wherein a fourth surface of the second semiconductor chip faces the first semiconductor chip, and second chip pads are formed on a third surface, opposite to the fourth surface, of the second semiconductor chip (Fig. 3 illustrates the surface arrangement as claimed in the annotated Fig. 3 below. Paragraph [0043-0044]).
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Regarding claim 16, OH in view of KIM teaches the semiconductor package of claim 15, OH further teaches further comprising: bonding wires (Fig. 3, #230 called bonding wires. Paragraph [0039) electrically connecting the second chip pads (Fig. 3, #310 called connection members. Paragraph [0039]) of the second semiconductor chip to second substrate pads (Fig. 3, #103 called second pads. Paragraph [0035]) of the package substrate (Fig. 3. Paragraph [0035]-OH discloses bonding wires 230 may be disposed between the other ends of the redistribution lines 209 and the second pads 103 of the package substrate 100, thereby electrically connecting the redistribution lines 209 to the second pads 103. For example, the package substrate 100 and the first semiconductor chip 200 may not be electrically connected to each other through the bonding wires 230. The bonding wires 230 may include, for example, gold (Au). Please also read paragraph [0036]).
Regarding claim 17, OH in view of KIM teaches the semiconductor package of claim 16, OH further teaches wherein the second substrate pads are provided on the bottom surface of the receiving groove (Fig. 3, illustrates second substrate pads #103 are provided on the bottom surface of the receiving groove. Paragraph [0025]).
Claim 12, is rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM and in further view of LEE (US 20210358882 A1), hereinafter referenced as LEE.
Regarding claim 12, OH in view of KIM teaches the semiconductor package of claim 11, OH in view of KIM fail to explicitly teach wherein the second cover portion of the underfill member covers a side surface of the adhesive film that is disposed below the second semiconductor chip.
However, LEE explicitly teaches wherein the second cover portion of the underfill member covers a side surface of the adhesive film that is disposed below the second semiconductor chip (Fig. 8A, illustrates a part of the adhesive film #12 meets the second underfill members #303 that is under the second semiconductor chip #300. Paragraph [0071]-LEE discloses the fourth surface 12_b of the adhesive film 12 included in the semiconductor chip mounting tape 10 may contact the top surface of the substrate 100 and the top surfaces and the sidewalls of the first and second semiconductor chips 200 and 300. The fourth surface 12_b of the adhesive film 12 may also contact the first and second underfill members 203 and 303.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH of having a semiconductor package, comprising: a package substrate having a receiving groove that has a predetermined depth from on an upper surface of the package substrate; a first semiconductor chip disposed in the receiving groove of the package substrate; a second semiconductor chip attached to an upper surface of the first semiconductor chip by an adhesive film to expose a portion of the upper surface of the first semiconductor chip, with the teachings of LEE of having wherein the second cover portion of the underfill member covers a side surface of the adhesive film that is disposed below the second semiconductor chip.
Wherein having OH’s a semiconductor package structure, wherein the second cover portion of the underfill member covers a side surface of the adhesive film that is disposed below the second semiconductor chip.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, prevent cracks and heat dissipation and minimum feature size, since both OH and LEE are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while LEE’s semiconductor structure system that provide semiconductor packages to prevent defects such as cracks from occurring in manufacturing a semiconductor package, which may improve reliability of the semiconductor package. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and LEE (US 20210358882 A1), Paragraphs [0103].
Claim 13, is rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM and in further view of KIM et al. (US 20220013501 A1), hereinafter referenced as KIM 1.
Regarding claim 13, OH in view of KIM teaches the semiconductor package of claim 11, OH in view of KIM fail to explicitly teach wherein a thickness of the second cover portion of the underfill member is within a range of 5 μm to 30 μm, inclusive.
However, KIM 1 explicitly teaches wherein a thickness of the second cover portion of the underfill member is within a range of 5 μm to 30 μm, inclusive (Fig. 1A. Paragraph [0055]-KIM 1 disclose the thickness of the second underfill layer 420 may range from about 3 μm to about 20 μm. Thus, thermal properties of the semiconductor package may be improved.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH in view of KIM of having a semiconductor package, comprising: a package substrate having an upper surface and a lower surface opposite the upper surface, wherein the package substrate has a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove of the package substrate, wherein a first surface of the first semiconductor chip faces the package substrate, and first chip pads are formed on the first surface; a second semiconductor chip attached to a second surface opposite to the first surface of the first semiconductor chip by an adhesive film, wherein the second semiconductor chip does not overlap a portion of the second surface of the first semiconductor chip, with the teachings of KIM 1 of having wherein a thickness of the second cover portion of the underfill member is within a range of about 5 μm to about 30 μm.
Wherein having OH’s a semiconductor package structure, wherein a thickness of the second cover portion of the underfill member is within a range of about 5 μm to about 30 μm.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances density and functionality of semiconductor dies, heat dissipation and minimum feature size, since both OH and KIM 1 are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while KIM’s 1 semiconductor structure system that thermal properties of the semiconductor package may be improved. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and KIM et al. (US 20220013501 A1), Paragraphs [0055]
Claim 14, is rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM and in further view of YU (US 20230063147 A1), hereinafter referenced as YU.
Regarding claim 14, OH in view of KIM teaches the semiconductor package of claim 11, OH in view of KIM fail to explicitly teach wherein the first semiconductor chip is mounted on first substrate pads via conductive bumps that are formed on the first chip pads of the first semiconductor chip, wherein the first substrate pads are disposed on the bottom surface of the receiving groove.
However, YU explicitly teaches wherein the first semiconductor chip (Fig. 1E, #220 called a second semiconductor chip. Paragraph [0036]) is mounted on first substrate pads via conductive bumps (Fig. 1E, illustrates first semiconductor chip #220 is mounted on first substrate pads #150 via conductive bumps #520. Paragraph [0065]-YU discloses second bumps 520 may be interposed between the interposer substrate 100 and the second semiconductor chip 220. For example, the second bumps 520 may be correspondingly coupled to the interposer pads 150 and the chip pads 225 of the second semiconductor chip 220. The second bumps 520 may include solder balls.) that are formed on the first chip pads (Fig. 1E, #225 called chip pads. Paragraph [0065]) of the first semiconductor chip (Fig. 1E. Paragraph [0065]), wherein the first substrate pads are disposed on the bottom surface of the receiving groove (Fig. 1E, illustrates wherein the first substrate pads #150 are disposed on the bottom surface of the receiving groove that receive the bumps #520. Paragraph [0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH in view of KIM of having a semiconductor package, comprising: a package substrate having an upper surface and a lower surface opposite the upper surface, wherein the package substrate has a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove of the package substrate, wherein a first surface of the first semiconductor chip faces the package substrate, and first chip pads are formed on the first surface; a second semiconductor chip attached to a second surface opposite to the first surface of the first semiconductor chip by an adhesive film, wherein the second semiconductor chip does not overlap a portion of the second surface of the first semiconductor chip, with the teachings of YU of having wherein the first semiconductor chip is mounted on first substrate pads via conductive bumps that are formed on the first chip pads of the first semiconductor chip, wherein the first substrate pads are disposed on the bottom surface of the receiving groove.
Wherein having OH’s a semiconductor package structure, wherein the first semiconductor chip is mounted on first substrate pads via conductive bumps that are formed on the first chip pads of the first semiconductor chip, wherein the first substrate pads are disposed on the bottom surface of the receiving groove.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, heat dissipation and minimum feature size, since both OH and YU are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while YU’s semiconductor structure system that the semiconductor package exhibit improved reliability. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and YU (20230063147), Paragraphs [0079]
Claim 18, is rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM and in further view of Lee et al. (US 20230130983 A1), hereinafter referenced as Lee 1.
Regarding claim 18, OH in view of KIM teaches the semiconductor package of claim 11, OH in view of KIM fail to explicitly teach further comprising: a dam structure that protrudes to have a predetermined height on the upper surface of the package substrate and extends along a circumference of the receiving groove to cover a portion of the underfill member that protrudes from the receiving groove.
However, Lee 1 explicitly teaches further comprising: a dam structure (Fig. 4, #140 called a dam structure. Paragraph [0093]) that protrudes to have a predetermined height on the upper surface of the package substrate (Fig. 4, illustrates the dam structures #140 are located on the upper surface of the first semiconductor substrate #111. Paragraph [0088-0089]) and extends along a circumference of the receiving groove to cover a portion of the underfill member (Fig. 4, #135 called underfill fillet. Paragraph [0045]) that protrudes from the receiving groove (Fig. 4, illustrates the underfill fillet #135 protrudes from the receiving groove #124. Paragraph 0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH in view of KIM of having a semiconductor package, comprising: a package substrate having an upper surface and a lower surface opposite the upper surface, wherein the package substrate has a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove of the package substrate, wherein a first surface of the first semiconductor chip faces the package substrate, and first chip pads are formed on the first surface; a second semiconductor chip attached to a second surface opposite to the first surface of the first semiconductor chip by an adhesive film, wherein the second semiconductor chip does not overlap a portion of the second surface of the first semiconductor chip, with the teachings of Lee 1 of having wherein further comprising: a dam structure that protrudes to have a predetermined height on the upper surface of the package substrate and extends along a circumference of the receiving groove to cover a portion of the underfill member that protrudes from the receiving groove.
Wherein having OH’s a semiconductor package structure, wherein further comprising: a dam structure that protrudes to have a predetermined height on the upper surface of the package substrate and extends along a circumference of the receiving groove to cover a portion of the underfill member that protrudes from the receiving groove.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances reliability, heat dissipation and minimum feature size, since both OH and Lee 1 are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while Lee 1’s semiconductor structure system improving adhesion strength of each component and/or preventing each component from physical strength deterioration due to deformation. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and Lee et al. (US 20230130983 A1), Paragraphs [0046]
Claim 19, is rejected under 35 U.S.C. 103 as being unpatentable over OH et al. (US 20190295986 A1), hereinafter referenced as OH in view of KIM et al. (US 20210057380 A1), hereinafter referenced as KIM and in further view of Yamagata (US 20050074921 A1), hereinafter referenced as Yamagata.
Regarding claim 19, OH in view of KIM 1 teaches the semiconductor package of claim 11, OH in view of KIM 1 fail to explicitly teach wherein the adhesive film includes a die attach film.
However, Yamagata explicitly teaches wherein the adhesive film includes a die attach film (Fig. 8. Paragraph [0046]-Yamagata discloses by using the die bonder and pushing up the support film 11 by the pushup collet 32 from the back side of the surface where the die-attach film 10 is provided, the support film 11 can be stretched so as to separate the adhesive film into the cut individual pieces at the cuts 10a.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to combine the teachings of OH in view of KIM of having a semiconductor package, comprising: a package substrate having an upper surface and a lower surface opposite the upper surface, wherein the package substrate has a receiving groove that has a predetermined depth from the upper surface; a first semiconductor chip disposed in the receiving groove of the package substrate, wherein a first surface of the first semiconductor chip faces the package substrate, and first chip pads are formed on the first surface; a second semiconductor chip attached to a second surface opposite to the first surface of the first semiconductor chip by an adhesive film, wherein the second semiconductor chip does not overlap a portion of the second surface of the first semiconductor chip, with the teachings of Yamagata of having wherein the adhesive film includes a die attach film.
Wherein having OH’s a semiconductor package structure, wherein the adhesive film includes a die attach film.
The motivation behind the modification would have been to obtain a semiconductor package structure system that enhances chip bonding without defects, heat dissipation and minimum feature size, since both OH and Yamagata are systems that relate to integrated semiconductor structure packages. Wherein OH’s semiconductor structure system to provide a semiconductor package with improved electrical characteristics, while Yamagata’s semiconductor structure system that enables mounting without the piece of adhesive film sticking out from the semiconductor chip, so a semiconductor package can be produced while suppressing interconnect defects and enables a semiconductor chip to be bonded to a substrate without sticking out of the film from the semiconductor chip. Please see OH et al. (US 20190295986 A1), Paragraphs [0006] and Yamagata (US 20050074921 A1), Paragraphs [0068 and 0070].
Conclusion
Listed below are the prior arts made of record and not relied upon but are considered pertinent to applicant`s disclosure.
(a) Ma et al. (US 20150130030 A1)- A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip...........Please see Fig. 1. Abstract.
(b) Hong et al. (US 20150130078 A1)- A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member disposed on the top surface of the first package........ ......... Fig. 1-2. Abstract.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/CHINEYERE WILLS-BURNS/Supervisory Patent Examiner, Art Unit 2673
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