DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in People’s Republic of China on 12/29/2023. It is noted, however, that applicant has not filed a certified copy of the CN202311850137.1 application as required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites a method for manufacturing a semiconductor structure comprising: growing a channel layer, a barrier layer and an n-type semiconductor layer on a substrate sequentially; etching a trench on the n-type semiconductor layer, wherein the trench penetrates through the n-type semiconductor layer; growing a sacrificial layer on the n-type semiconductor layer and in the trench; etching the sacrificial layer; and growing a p-type semiconductor layer on the n-type semiconductor layer and in the trench, wherein before performing the growing a p-type semiconductor layer on the n-type semiconductor layer and in the trench, the growing a sacrificial layer on the n-type semiconductor layer and in the trench and the etching the sacrificial layer is repeated N times until a concentration of an impurity element on a surface of the barrier layer below the trench is less than a preset value (emphasis added).
As noted above, 35 USC § 112(a) requires that the specification contain a written description of the invention in full, clear, concise, and exact terms. Claim 1 recites repeating deposition and etch steps N times, without limiting the number of repetitions. Claim 1 also requires reducing an impurity element of a barrier layer to below a preset value, without defining the particular preset value. The specification fails to define or limit either the number of repetitions, or the impurity concentration. Therefore, the specification as originally filed fails to contain a written description of the invention in full, clear, concise, and exact terms.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “N number of times” in claim 1 is a relative term which renders the claim indefinite. The term “N” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The tern “N number of times” can mean any natural number of times, and the endpoint for this step is not clear enough so it can be repeated an infinite number of times.
The term “preset value ” in claim 1 is a relative term which renders the claim indefinite. The term “preset value” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The term “preset value” refers to an impurity concentration that is unknown. The concentration value would need to be defined and supported in the specification to define the metes and bounds of the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 8, 11, 12, 17, 18, and 20 are rejected under U.S.C 103 as being unpatentable over Cheng (PG Pub. No US 2019/0311914 A1) in view of Blanchard (PG Pub No US 2003/0181010 A1).
Regarding claim 1, Cheng teaches, a method for manufacturing a semiconductor structure (¶0048, Fig 10), comprising:
growing a channel layer(13), a barrier layer(14), and an n-type semiconductor layer (¶0015: thin film n-type layer 15) on a substrate sequentially;
etching a trench on the n-type semiconductor layer, wherein the trench (Fig 10: groove H opening) penetrates through the n-type semiconductor layer (groove opening etched in film layer 15);
and growing a p-type semiconductor layer (31) on the n-type semiconductor layer (15) and in the trench (groove opening in 15),
Cheng does not teach growing a sacrificial layer on the n-type semiconductor layer and in the trench; etching the sacrificial layer; wherein before performing the growing a p-type semiconductor layer on the n-type semiconductor layer and in the trench, the growing a sacrificial layer on the n-type semiconductor layer and in the trench and the etching the sacrificial layer is repeated N times until a concentration of an impurity element on a surface of the barrier layer below the trench is less than a preset value. Blanchard (¶0025-¶0028, Fig. 5b-5d) teaches a method including:
growing a sacrificial layer(¶0025: 524.sub.1) on the n-type semiconductor and in the trench (¶0027, Fig. 5b)
etching the sacrificial layer (¶0025)
wherein before performing the growing a p-type semiconductor layer on the n-type semiconductor layer and in the trench the growing a sacrificial layer on the n-type semiconductor layer and in the trench and the etching the sacrificial layer is repeated N times (¶0025-0028, Fig. 5a-5d: growing/etching layer xx repeated at least once) until a concentration of an impurity element on a surface of the barrier layer below the trench is less than a preset value (implicit: forming and removing layer 524.sub.1 erodes underlying N- layer, such that an amount of impurity in N- is reduced).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the method of manufacturing a semiconductor structure of Cheng with the method of using a sacrificial layer and repeat etching before applying the p-type layer, as means that at least one region of conductivity type opposite to the conductivity type of the epitaxial layer is formed over the voltage sustaining region to define a junction therebetween (Blanchard ¶0013).
Regarding claim 2, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein the trench penetrates through the n-type semiconductor layer(15) and partially penetrates through the barrier layer(14).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to partially penetrate the layer at the bottom of the trench if it is using an etch technique.
Regarding claim 8, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1,
Cheng and Blanchard do not teach wherein before etching the trench on the n-type semiconductor layer, the method further comprises: disposing a first insertion layer on the n-type semiconductor layer, wherein a material of the first insertion layer comprises AlGaN.
Cheng teaches an AlGaN buffer layer(¶0035: layer 12) that was inserted prior to on the device. It would have been obvious to one of ordinary skill in the art at the time the invention was filed to rearrange the AlGaN layer on the semiconductor device stack as means to decrease temperature after a trench is etched and another semiconductor layer is grown, thereby increasing the performance (Cheng PG Pub. No. US 2022/0246752 A1).
Regarding claim 11, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein the sacrificial layer (Blanchard, ¶0025, Fig 5b: 524.sub.1) is conformally grown on the n-type semiconductor layer and in the trench (Blanchard, ¶0026, Fig 5b:520.sub.1). (Blanchard Fig5b: 524.sub.1 is grown on N- and in 520.sub.1).
Regarding claim 12, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein a surface, away from the substrate (Blanchard, Fig 5b:N+), of the sacrificial layer is a plane (Blanchard, Fig 5b: a surface of 524.sub.1, opposite N+ is a plane).
Regarding claim 17, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein the p-type semiconductor layer (Cheng, Fig 10: 31) is conformally grown on the n-type semiconductor layer (Cheng, Fig 10: thin film 15) and in the trench. ( 31 grown on top of 15 and in the opening of 15).
Regarding claim 18, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein a surface, away from the substrate (Cheng Fig 10: 10), of the p-type semiconductor (31) layer is a plane. (surface of 31, opposite 10 and away from the trench, is a plane).
Regarding claim 20, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, further comprising: etching the n-type semiconductor layer (Cheng, 15) to expose the barrier layer (Cheng, 14), and form a source region (Cheng 21) and a drain region(Cheng, 22), disposing a source electrode in the source region, disposing a drain electrode in the drain region, and disposing a gate electrode (Cheng, 23) on the p-type semiconductor layer located on the trench. (Cheng Fig 10, ¶0042-¶0043 etching 15 to expose 14, then 21, 22 and 23 are respectively formed).
Claims 3,4,5 and 13 are rejected under U.S.C 103 as being unpatentable over Cheng (PG Pub. No US 2019/0311914 A1) and Blanchard (PG Pub No US 2003/0181010 A1) as applied to claim 1 above, and further in view of Bour (PG Pub. No. US 20140045306 A1).
Regarding claim 3, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, wherein a method for etching the trench comprises etching (Cheng, ¶0048).
Blanchard further teaches a trench is dry etched (¶0025).
Cheng in view of Blanchard fails to teach wherein etching the trench comprises in-situ etching.
Bour teaches a method for etching the trench (113) comprises in-situ etching (¶0032, Fig 1C).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the in-situ method of Bour in the method of manufacturing of Cheng and Blanchard as means to improve the reliability and performance associated with the regrowth interface (Bour 0002).
Regarding claim 4, Cheng in view of Blanchard and Bour teaches the method for manufacturing the semiconductor structure according to claim 3, wherein the in-situ etching comprises dry etching(Bour, ¶0032: in-situ etching performed in a gaseous environment, meeting the broadest reasonable interpretation of “dry etching”).
Regarding claim 5, Cheng in view of Blanchard and Bour teaches the method for manufacturing the semiconductor structure according to claim 3,
Blanchard further teaches forming a trench by dry etching (¶ 0025).
Cheng in view of Blanchard and Bour fails to teach wherein a gas atmosphere for etching the trench comprises one or a combination of more of Cl2, H2, HCl and tertiarybutylchloride (TBCl).
However, Bour teaches the in-situ etch is performed in a hydrogen atmosphere (¶0032: high temperature, hydrogen rich environment).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the hydrogen atmosphere of Bour with the method of Cheng in view of Blanchard, as means to prevent the decomposition of the semiconductor materials (Bour, ¶ 0032).
Regarding claim 13, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, including etching the sacrificial layer (Blanchard, ¶ 0025).
Cheng in view of Blanchard does not teach wherein etching the sacrificial layer comprises in-situ etching.
Bour teaches etching the trench (113) using an in-situ etching method (¶ 0032).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the same etching process as means to improve the reliability and performance associated with the regrowth interfaces (Blanchard, ¶0002).
Claim 9 is rejected under U.S.C 103 as being unpatentable over Cheng (PG Pub. No US 2019/0311914 A1) and Blanchard (PG Pub No US 2003/0181010 A1) as applied to claim 1 above, and further in view of Jones (PG Pub. No. US 20210111254 A1).
Regarding claim 9, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, including growing a channel layer, a barrier layer and an n-type semiconductor layer on a substrate sequentially (Cheng, fig. 7: layers 13/14/15 sequentially formed on substrate 10)
Cheng in view of Blanchard fails to teach the sequence further comprises: growing the barrier layer, a second insertion layer and the n-type semiconductor layer on the substrate sequentially, wherein the second insertion layer is an unintentional doped layer.
Jones teaches a method of forming a HEMT device (figs. 1-12: 100) including growing a barrier layer and an insertion layer sequentially (¶0052: forming barrier layer 22 comprises growing a first sub-layer and at least one unintentionally doped sub-layer).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to combine the method of Cheng and Blanchard with the unintentionally doped insertion layer taught in Jones, as means to decrease conductivity further away from the channel layer (¶0055).
Claim 10 is rejected under U.S.C 103 as being unpatentable over Cheng (PG Pub. No US 2019/0311914 A1) and Blanchard (PG Pub No US 2003/0181010 A1) as applied to claim 1 above, and further in view of Sato (PG Pub. No. US 2011/0095337 A1)
Regarding claim 10, Cheng in view of Blanchard teaches the method for manufacturing the semiconductor structure according to claim 1, including an n-type layer (Cheng, 15). Cheng in view of Blanchard further teaches the n-type layer comprises nitride (Cheng, ¶ 0049).
Cheng in view of Blanchard fails to teach wherein a material of the n-type semiconductor layer comprises at least one of n-type GaN, n-type AlGaN or n-type AlInGaN.
Sato teaches a semiconductor structure (Fig. 3) including an n-type layer (¶ 0032: 13, similar to 15 of Cheng), wherein a material of the n-type semiconductor layer comprises at least one of n-type GaN, n-type AlGaN or n-type AlInGaN (¶ 0032: 13 comprises n-type GaN).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the n-type layer taught by Cheng and Blanchard with GaN, as a means to improve the reliability of the HEMT device by making it operate to control the surface charge and reduce the electrode resistance (Sato, ¶ 0034).
Claim 19, is rejected under U.S.C 103 as being unpatentable over Cheng (PG Pub. No US 2019/0311914 A1) and Blanchard (PG Pub No US 2003/0181010 A1) as applied to claim 1 above, and further in view of Cheng (PG Pub. No. US 2015/0053921 A1, hereinafter ‘Cheng2’).
Regarding claim 19, Cheng in view of Blanchard teaches, the method for manufacturing the semiconductor structure according to claim 1, including a p-type semiconductor layer (Cheng, 31). Cheng in view of Blanchard further teaches the p-type semiconductor layer comprises GaN (Cheng, ¶ 0037).
Cheng in view of Blanchard fails to teach the p-type semiconductor layer comprises at least one of p-type diamond, p-type NiO, p-type single crystal GaN or p-type polycrystalline GaN.
Cheng2 teaches wherein a material of a p-type semiconductor layer (¶0069, Fig 11g: 9) comprises at least one of p-type diamond, p-type NiO, p-type GaN or p-type polycrystalline GaN.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the p-type semiconductor layer taught by Cheng and Blanchard with at least one of p-type diamond, p-type NiO, or p-type polycrystalline GaN, as a means to provide a gate structure of the resulting device (¶ 0070).
Allowable Subject Matter
Claims 6,7,14, 15 and 16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LYTESHIA M PRICE whose telephone number is (571)270-0132. The examiner can normally be reached 8am-5pm.
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/Lyteshia Price./Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
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