DETAILED ACTION
The action is responsive to the following communications: the Application filed March 28, 2024 and the information disclosure statement (IDS) filed March 28, 2024 and July 23, 2025.
Claims 1-32 are pending. Claims 3-6 and 14-15 are withdrawn from consideration as being drawn to non-elected inventions without traverse. Claims 16-23 have been cancelled. Claims 1 and 7 are independent.
Notice of Pre-AIA or AIA Status
The present application is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 28, 2024 and July 23, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-13 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Peng et al. (US 7,636,268) in view of Singh et al. (US 2019/0066772).
Regarding independent claim 7, the prior art of Peng et al. teach an electronic device including a memory, the electronic device comprising:
a plurality of word lines selectively driven by a decoder (FIG. 1: 116, a word line driver which is driven by a decoder is an inherent characteristic in memory array such as FIG. 2 and applicant’s prior art, FIG. 1);
each word line having an underdrive circuit (FIG. 1: 114) coupled thereto, wherein that underdrive circuit includes a first transistor (102 or 104) coupled to that word line (110 WL), the first transistor being a replica of a pull-down transistor or a pass gate transistor of a bitcell of the memory (see e.g., col. 2, lines 54-60: … The NMOS device 102, 104 … are referred to as “replica access transistors” …).
Peng et al. do not explicitly teach claimed a bleeder transistor.
However, claimed a bleeder transistor is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Singh et al. teach each word line having a first bleeder transistor (e.g., FIG. 3A: N2_1 or N2_2) that is source/drain coupled between that word line and ground and having a gate driven by a first read assist control signal (rd_ast).
Peng and Singh are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Peng with the specified features of Singh because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Singh et al. to the teaching of Peng et al. such that a memory, as taught by Peng et al., utilizes a pull-down transistor, as taught by Singh et al., for the purpose of activating pulling down word line voltages, thereby assisting memory read operations.
Regarding claims 8 and 11, Peng et al and Singh et al., as combined, teach the limitations of claim 7.
Peng et al. further teach the first transistor is source/drain coupled between the word line and ground (FIG. 1: 102) and has a gate driven by a supply voltage.
Peng et al. are silent with respect to a gate driven by a supply voltage.
Singh et al. teach a transistor within a read assist circuitry, the gate of the transistor is driven by a supply voltage (see FIG. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Singh et al. for the same purpose of performing improved read operations.
Regarding claims 9 and 12, Peng et al and Singh et al., as combined, teach the limitations of claim 7.
Peng et al. further teach the first transistor is source/drain coupled between the word line and ground (FIG. 1: 102) and has a gate driven by a second read assist control signal.
Peng et al. are silent with respect to a gate driven by a second read assist control signal.
Singh et al. teach a transistor within a read assist circuitry, the gate of the transistor is driven by a read assist control signal (see FIG. 2B).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Singh et al. for the same purpose of performing improved read operations.
Regarding claim 10, Peng et al and Singh et al., as combined, teach the limitations of claim 7.
Peng et al. are silent with respect to the first transistor for each word line is coupled between that word line and an immediately adjacent word line.
Singh et al. teach the deficiencies, the first transistor for each word line is coupled between that word line and an immediately adjacent word line (see FIG. 3B).
It would have been obvious to one of ordinary skill in the art before the effective filing date to further modify the invention of Singh et al. for the same purpose of performing improved read operations.
Regarding claim 13, Peng et al and Singh et al., as combined, teach the limitations of claim 7.
Peng’s the first read assist control signal do not explicitly teach the first read assist control signal is compensated for process, voltage, and temperature variance.
However, PVT immunized read assisting is a well-known technology for a type of memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in PVT immunized circuitry because these conventional technology are well established in the art of the memory devices.
Allowable Subject Matter
Claims 1-2 are allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
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