Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 05/11/2026. Applicant's election with traverse of Species I (Figures 1-2), claims 1-20, in the reply filed on 05/11/2026 is acknowledged, there being no allowable generic or linking claim. Currently, claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election with traverse of Species IA, claims 1-20, in the reply filed on 05/11/2026 is acknowledged.
The first traversal is on the ground(s) that the examination of all of claims 1-20 would not present an undue burden on the Examiner, and respectfully request reconsideration and withdrawal of the Restriction Requirement.
This is not found persuasive and the Examiner has already established burden (as defined in M.P.E.P. 808.02) in the restriction requirement dated 05/07/2026. There is a search and/or examination burden for the patentably distinct species or device/method claims, wherein they require a different field of search (e.g., searching different classes/subclasses or electronic resources or non-patent language, or deploying different search queries); and/or the prior art applicable to one invention would not likely be applicable to another; and/or the inventions are likely to raise different non-prior art issues under 35 U.S.C 101 and/or 35 U.S.C 112, first paragraph. Therefore, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being obvious over KANG et al (US 20220068784 A1, hereinafter as “K4”) in view of KANG et al (US 20220052006 A1, hereinafter as “K6”).
Regarding claim 1, Figure 12 of K4 disclose a semiconductor package, comprising:
a semiconductor chip (200, [0020]);
a redistribution layer (411, [0039]) on the semiconductor chip;
a protection pattern (412, [0039]) covering the redistribution layer; and
a connection terminal (1160, [0071]) on the redistribution layer,
wherein the redistribution layer includes a redistribution pad (420+pad between 420 and 1160, [0040]) on a top surface of the redistribution layer,
the redistribution pad includes a first pad (420) and a second pad (pad between 420 and 1160) on the first pad, the second pad has a side surface that is inclined (please see the inclination in Figure 7) and that extends to a top surface of the first pad (420), and
the protection pattern (412) has a side surface that is inclined (please see the inclination in Figure 7) and that extends to the top surface of the first pad (420).
K4 does not teach that the protection pattern (412) is spaced apart from the side surface of the second pad (layer between 420 and 1160).
However, K6 is a pertinent art which teaches a semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. Figure 1/2 of K6 taches such UBM structure 120 ([0028]) with a first portion 121 and a second portion 122 under the first portion and a connection bump 160 ([0022]), wherein the connection bump includes a first portion on the first portion 121 and a portion separating the first portion 121 from a protection layer 111.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of K4 such that t the protection pattern (412) is spaced apart from the side surface of the second pad (pad between 420 and 1160, Figure 12 of K4) according to the teaching of K6 in order to form an connectivity with improved adhesin and reliability ([0003], K6).
Regarding claim 2, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein the connection terminal (1160) includes a first portion on the second pad and a second portion extending between the side surface of the second pad and the side surface of the protection pattern (please see Figures 1B and 2 of K6).
Regarding claim 3, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 2, wherein the second portion is in contact with the top surface of the first pad (please see Figure 1B and 2 of K6).
Regarding claim 4, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 2, wherein the second portion has a width that decreases as a distance to the first pad decreases (please see Figure 2 of K6).
Regarding claim 5, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 2, wherein the connection terminal further includes a third portion extending from the second portion to a region between a bottom surface of the protection pattern and the top surface of the first pad (please see Figure 2 of K6).
Regarding claim 6, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein a width of the second pad increases as a distance from the top surface of the first pad increases (please see Figure 2 of K6).
Regarding claim 7, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein a width of the second pad decreases as a distance from the top surface of the first pad increases (please see Figure 2 of K6).
Regarding claim 8, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein a top surface of the protection pattern (412, Figure 12 of K4) is higher than a top surface of the second pad (pad between 1160 and 420).
Regarding claim 9, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein the protection pattern (412, Figure 12 of K4) covers a side surface of the first pad and a portion of the top surface of the first pad, and the protection pattern exposes the second pad (pad between 1160 and 420).
Regarding claim 10, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein the second pad (pad between 1160 and 420, Figure 12 of K4) vertically overlaps the first pad (420).
Regarding claim 11, Figure 12 of K4 discloses that the semiconductor package of claim 1, wherein a width of the first pad (420) is larger than a width of the second pad (pad between 1160 and 420).
Regarding claim 12, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein a roughness of the side surface of the protection pattern is greater than a roughness of the side surface of the second pad (please see Figure 2 of K6).
Regarding claim 13, Figure 12 of K4 in view of K6 does not explicitly teaches that the semiconductor package of claim 1, wherein the first pad and the second pad include different metallic materials from each other.
However, the Examiner takes an official notes that such limitations are very well known in pertinent prior arts for pad and under bump metal.
Regarding claim 14, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 1, wherein the side surface of the second pad is inclined at an angle of 3o to 20o to a direction perpendicular to the top surface of the first pad (please see Figure 2 of K6).
Regarding claim 15, Figure 12 of K4 discloses a semiconductor package, comprising:
a lower redistribution layer (300, [0020]);
a first semiconductor chip (200, [0020]) on the lower redistribution layer;
an upper redistribution layer (411, [0039]) on the first semiconductor chip, the upper redistribution layer including a redistribution pad (420+layer between 420 and 1160) on a top surface of the upper redistribution layer;
a second semiconductor chip (1120, [0070]) on the upper redistribution layer;
a connection terminal (1160, [0071]) electrically connecting the second semiconductor chip to the upper redistribution layer; and
a protection pattern (412, [0039]) on the upper redistribution layer, wherein the redistribution pad includes a first pad (420, [0037]) and a second pad (layer between 420 and 1160 on the first pad.
K4 does not teach that the protection pattern (412) has a side surface on the first pad and the side surface of the protection pattern is spaced apart from a side surface of the second pad, and the connection terminal (1160) includes a first portion on a top surface of the second pad and a second portion between the side surface of the second pad and the side surface of the protection pattern.
However, K6 is a pertinent art which teaches a semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. Figure 1 of K6 taches such UBM structure 120 ([0028]) with a first portion 121 and a second portion 122 under the first portion and a connection bump 160 ([0022]), wherein the connection bump includes a first portion on the first portion 121 and a second portion between the first portion 122 and a protective layer.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of K4 such that the protection pattern (412) has a side surface on the first pad and the side surface of the protection pattern is spaced apart from a side surface of the second pad, and the connection terminal (1160) includes a first portion on a top surface of the second pad and a second portion between the side surface of the second pad and the side surface of the protection pattern according to the teaching of K6 in order to form an connectivity with improved adhesin and reliability ([0003], K6).
Regarding claim 16, Figure 12 of K4 discloses that the semiconductor package of claim 15, wherein a width of the first pad (420) is larger than a width of the second pad (layer between 420 and 1160), and the first pad and the second pad vertically overlap each other.
Regarding claim 17, Figure 12 of K4 in view of K6 teaches that the semiconductor package of claim 15, wherein the second portion extends in an inclined direction to a top surface of the first pad, and the second portion is in contact with the top surface of the first pad (please see Figure 1B/2A of K6).
Regarding claim 18, Figure 12 of K4 in view of K6 do not explicitly teach that the semiconductor package of claim 15, wherein a vertical length of the second portion ranges from 3 um to 5 um, and a horizontal width of the second portion ranges from 1 um to 4 um.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges for an improved connection with lower cost since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 19, Figure 12 of K4 in view of K6 do not explicitly teach that the semiconductor package of claim 15, wherein the first pad includes copper (Cu), and the second pad includes nickel (Ni) or gold (Au).
However, the Examiner takes an official notes that such materials are very well known in pertinent prior arts for pad and under bump metal.
Claim 20 is rejected under 35 U.S.C. 103 as being obvious over KANG et al (US 20220068784 A1, hereinafter as “K4”) in view of KANG et al (US 20220052006 A1, hereinafter as “K6”) and Jun et al (US 20220020713 A1).
Regarding claim 20, Figure 12 of K4 discloses a semiconductor package, comprising:
a lower redistribution layer (300, [0020]);
a logic chip (200, [0020]) on the lower redistribution layer;
a connection substrate (110, [0022]) on the lower redistribution layer enclosing the logic chip in a plan view;
a mold layer (210, [0026]) covering the logic chip and the connection substrate;
an upper redistribution layer (411, [0039]) on the mold layer, the upper redistribution layer including redistribution pads;
a protection pattern (412, [0039]) covering the upper redistribution layer;
a semiconductor chip (1120, [0070]) on the upper redistribution layer; and
connection terminals (1160, [0071]) on corresponding ones of the redistribution pads, the connection terminals between the upper redistribution layer (411) and the memory chip (1120), wherein each of the redistribution pads (420+pad between 1160 and 420) includes a first pad (420) and a second pad (pad between 1160 and 420) on the first pad, the protection pattern (412) covers the first pad (420) and is horizontally spaced apart from the second pad, each of the connection terminals include a first portion on the second pad and a second portion extending between the second pad and the protection pattern, and the second pad and the protection pattern have side surfaces that are inclined and that extend to a top surface of the first pad, and the second pad (pad between 1160 and 420) and the protection pattern (412) have side surfaces (please see Figure 7 for clarity) that are inclined and that extend to a top surface of the first pad (420).
K4 does not teach that the protection pattern (412) is horizontally spaced apart from the second pad, each of the connection terminals (1160) include a first portion on the second pad and a second portion extending between the second pad and the protection pattern (412).
However, K6 is a pertinent art which teaches a semiconductor package includes a redistribution structure including an insulating layer and a redistribution layer on the insulating layer, and having a first surface and a second surface opposing the first surface, and an under-bump metal (UBM) structure including an UBM pad protruding from the first surface of the redistribution structure, and an UBM via penetrating through the insulating layer and connecting the redistribution layer and the UBM pad. Figure 1 of K6 taches such UBM structure 120 ([0028]) with a first portion 121 and a second portion 122 under the first portion and a connection bump 160 ([0022]), wherein the connection bump includes a first portion on the first portion 121 and a second portion between the first portion 122 and a protective layer.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package of K4 such that the protection pattern (412, Figure 1 of K4) is horizontally spaced apart from the second pad, each of the connection terminals (1160) include a first portion on the second pad and a second portion extending between the second pad and the protection pattern (412) according to the teaching of K6 in order to form an connectivity with improved adhesin and reliability ([0003], K6).
K4 does no teach that the semiconductor chip (1120) is a memory chip.
However, Jun is a pertinent art which teaches a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad. Figure 14 of Jun teaches such a semiconductor package wherein semiconductor chips such as 100 and 200 are packaged and Jun teaches that the semiconductor chips 100 and 200 may be memory chip for forming a memory device.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a memory chip in the semiconductor chip (1120, Figure 1 of K4) according to the teaching of Jun in order to make a memory device with improved packaging and high reliability.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/Primary Examiner, Art Unit 2813
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