Notice of Pre-AIA or AIA Status1
DETAILED ACTION
Currently, claims 1-21 are pending and examined below.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 03/28/2024 ("03-28-24 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 03-28-24 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INTEGRATED CIRCUIT (IC) HAVING CONDUCTIVE SCRIBELANE STRUCTURES IN FIRST SCRIBELANE PORTION WITH HIGH-VOLTAGE ROBUSTNESS
A. Prior-art rejections based on Lee
Claim Rejections - 35 USC § 1022
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0103070 A1 to Lee et al. ("Lee).
Fig. 5 of Lee has been annotated to support the rejection below:
[AltContent: textbox (Col2)][AltContent: textbox (Col1)][AltContent: textbox (CS4)][AltContent: arrow][AltContent: arrow][AltContent: textbox (SCR3e)][AltContent: textbox (114)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (CS3)][AltContent: textbox (D2)][AltContent: arrow][AltContent: textbox (D1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (SCR2)][AltContent: textbox (SCR1)][AltContent: arrow][AltContent: arrow][AltContent: textbox (CS2)][AltContent: arrow][AltContent: textbox (CS1)]
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Regarding independent claim 1, Lee teaches a semiconductor device 100b (para [0044] - “Referring to FIGS. 5 and 6, a semiconductor device 100b may include a substrate 102, and a test element group 110b and a guard ring 120, which are arranged on the substrate 102.”; para [0049] - “The first semiconductor chip 210 or one or more of the second semiconductor chips 300 may be the semiconductor chips SC, SCa, and SCb described with reference to FIGS. 1 to 6.”) comprising:
a semiconductor substrate 102 having a first cut side CS1 and an opposite second cut side CS2;
a circuit Scb (para [0081] discloses semiconductor chip SCb”; Fig. 7 shows an example of a semiconductor chip with circuits 203, 202, 204 in the semiconductor substrate 200 or circuits 210, 300 over the semiconductor substrate 200.) formed in or over the semiconductor substrate 102 between the first and second cut sides CS1 and CS2; and
a first scribelane portion SCR1 between the circuit Scb and the first cut side CS1 and a second scribelane portion SCR2 between the circuit Scb and the second cut side CS2, the first scribelane portion SCR1 including conductive scribelane structures 114 (para [0078] - “test pad 114”), and the second scribelane portion SCR2 being devoid of conductive scribelane structures 114.
Regarding claim 2, Lee teaches the semiconductor substrate 102 that has a third cut side CS3 and a fourth cut side CS4 opposite to the third cut side CS3, a third scribelane portion SCR3 between the third cut side CS3 and the circuit SCb, and a fourth scribelane portion SCR4 between the fourth cut side CS4 and the circuit SCb, the third and fourth scribelane portions SCR3, SCR4 devoid of conductive scribelane structures 114 (of SCR1).
Regarding claim 3, Lee teaches the circuit Scb that comprises a sensor circuit portion 212 (image sensor; para [0066] - “The first and second substrates 212 and 302 may include a plurality of different types of individual devices on the active surfaces thereof. The plurality of individual devices may include various microelectronic devices such as a MOSFET such as a CMOS) transistor, an image sensor such as an LSI, a CIS, etc., a micro-electro-mechanical system (EMS), an active device and/or a passive device, etc.”) and an interface circuit portion 302.
Regarding claim 4, a limitation of “configured to operate in an electric field from a high voltage conductor” does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by Lee as it is directed to a capability of the sensor circuit portion. The image sensor of Lee is capable of operating in an electric field from a high voltage conductor, because the image sensor has the same structure as claimed.
Regarding claim 6, Lee teaches the first scribelane portion SCR1 that is between a plurality of bond pads 118 (para [0046] - “second pads 118”) and the first cut side CS1.
Regarding claim 7, Lee teaches a scribe seal 120 surrounding the circuit SCb, the scribe seal 120 covered by a protective overcoat (para [0063] - “Insulating layers are arranged on the upper and lower surfaces of the guard ring 120 to electrically insulate the test element group 110, 110a and 110b.”).
Regarding independent claim 8, Lee teaches a method of fabricating an integrated circuit (IC), the method comprising:
processing a semiconductor wafer 102 (para [0023] - “The substrate 102 may include or be formed of silicon (Si).”; para [0027] - “The test element group 110 may be a pattern, or circuit (e.g., test circuit), for testing a manufacturing process of a semiconductor device and characteristics of the completely manufactured semiconductor device, for example, prior to singulation of the semiconductor device from the wafer.”) in a fabrication flow having a sequence of process stages for creating a plurality of semiconductor dies SCb (para [0049]; Fig. 5 shows four semiconductor chips SCb.) each containing an instance of the IC, the semiconductor wafer 102 providing a substrate for the IC, the processing including forming scribelanes SCR1, SCR2 (para [0025] - “…a scribe lane region SCR may surround an element region of each single semiconductor chip SC.”) extending in a first direction D1, a first subset SCR1 of scribelanes including conductive scribelane structures 114 and a second subset SCR2 of the scribelanes SCR2 interleaved with the first subset SCR2 and being devoid of conductive scribelane structures 114 (of SCR1) and
singulating the plurality of semiconductor dies SCb in a dicing operation (para [0032] - “For example, during cutting of the wafer, a portion of each test pad 114 may be cut, and each test pad may be split into two separate pieces on two separate singulated semiconductor chips.”; para [0078]).
Regarding claim 9, Lee teaches the scribelands SCR1, SCR2 that are first scribelanes SCR1, SCR2 and further comprising forming second scribelanes SCR3, SCR4 extending in a different second direction D2, wherein the second scribelanes SCR3, SCR4 are devoid of conductive scribelane structures 114 (of SCR1).
Regarding claim 10, Lee teaches the semiconductor dies SCb have a first side including bond pads 118 and opposing second side having no bond pads;
the scribelanes of the first subset SCR1 are located between corresponding first and second adjacent columns Col1, Col2 of the semiconductor dies SCb; and
the first sides of the semiconductor dies SCb of the first column Col1 face the first sides of the semiconductor dies SCb of the second column Col2.
Regarding claim 11, Lee teaches the scribelanes of the first subset SCR1 are located between corresponding first and second adjacent columns Col1, Col2 of the semiconductor dies SCb; and
the semiconductor dies SCb of the first column Col1 are identical to and rotated 180° with respect to the semiconductor dies SCb of the second column Col2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Patent No. US 11,322,433 B2 to Tuncer et al. (“Tuncer”) (cited in the 03-28-24 IDS).
Regarding independent claim 16, Lee teaches a semiconductor die 100b (para [0044] - “Referring to FIGS. 5 and 6, a semiconductor device 100b may include a substrate 102, and a test element group 110b and a guard ring 120, which are arranged on the substrate 102.”; para [0049] - “The first semiconductor chip 210 or one or more of the second semiconductor chips 300 may be the semiconductor chips SC, SCa, and SCb described with reference to FIGS. 1 to 6.”) having a first cut side CS1 and an opposite second cut side CS2;
a circuit Scb (para [0081] discloses semiconductor chip SCb”; Fig. 7 shows an example of a semiconductor chip with circuits 203, 202, 204 in the semiconductor substrate 200 or circuits 210, 300 over the semiconductor substrate 200.) between the first and second cut sides CS1 and CS2, the circuit Scb including a first circuit portion and a second circuit portion,
a first scribelane portion SCR1 between the circuit Scb and the first cut side CS1 and a second scribelane portion SCR2 between the circuit Scb and the second cut side CS2, the first scribelane portion SCR1 including conductive scribelane structures 114 (para [0078] - “test pad 114”), and the second scribelane portion SCR2 being devoid of conductive scribelane structures 114.
Lee does not teach a package integrated circuit comprising first package leads on a first side of a device package and second package leads on an opposite second side of the device package.
However, Tuncer teaches a package integrated circuit (IC) (see Fig. 2C), comprising:
first package leads 204A-204D (col. 6, ln 23-40 - “terminals 204A-204D and 204E-204H”) on a first side of a device package 200 and second package leads 204E, 204H on an opposite second side of the device package;
a semiconductor die 208 (col. 6, ln 23-40 - “die 208”) having a first cut side and an opposite second cut side;
a circuit (col. 2, ln 29-65) located between the first and second cut sides, the circuit including a first circuit portion and a second circuit portion, the semiconductor die 208 located between the first package leads 204A-204D and the second package leads 204E, 204H;
a lead frame portion 250 (col. 6, ln 1-22 - “conductive pathway 250”) over or a lead frame portion 205 (col. 5, ln 30-61 - “The package 200 includes a die pad 205…”) under the semiconductor die 208, the lead frame portion 250 or 205 extending over the second cut side toward the first cut side and ending over the second circuit portion;
bond pads 218 between the first circuit portion and the first cut side; and
bond wires 252 (col. 5, ln 30-61 - “bond wires 252”) connected between the bond pads 218 and the second package leads 204E, 204H.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the semiconductor device of Lee with the lead frame having die pad and leads as taught by Tuncer so as to implement the semiconductor device in a wire-bonded package (Tuncer, col. 2, ln 29-65) to couple to printed circuit board.
Regarding claim 17, the combination of Lee and Tuncer teaches a current loop in the lead frame portion 250.
Regarding claim 18, the combination of Lee and Tuncer teaches the semiconductor die 208 that is devoid of bond pads under or over the lead frame portion.
Regarding claim 19, a limitation of “configured to have a DC voltage of at least 300 V with respect to the semiconductor die” does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by the combination of Lee and Tuncer as it is directed to a capability of the lead frame portion. The lead frame portion taught Tuncer of the combination above is capable of having a DC voltage of at least 300 V with respect to the semiconductor die, because it has the same structure as claimed.
Regarding claim 21, Lee of the combination above teaches the semiconductor substrate 102 that has a third cut side CS3 and a fourth cut side CS4 opposite to the third cut side CS3, a third scribelane portion SCR3 between the third cut side CS3 and the circuit SCb, and a fourth scribelane portion SCR4 between the fourth cut side CS4 and the circuit SCb, the third and fourth scribelane portions SCR3, SCR4 devoid of conductive scribelane structures 114 (of SCR1).
B. Prior-art rejections based on Sugiyama
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 8, 9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2007/0203662 A1 to Sugiyama et al. ("Sugiyama”).
Figs. 1, 3A and 3B of Sugiyama have been annotated to support the rejection below:
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Regarding independent claim 1, Sugiyama teaches a semiconductor device (see Fig. 1 as well as Figs. 3A and 3B), comprising:
a semiconductor substrate a (see Fig. 1) having a first cut side CS1 and an opposite second cut side CS2;
a circuit (see Fig. 1) formed in or over the semiconductor substrate a between the first and second cut sides CS1, CS2; and
a first scribelane portion SP1 between the circuit and the first cut side CS1 and a second scribelane portion SP2 between the circuit and the second cut side CS2, the first scribelane portion SP1 including conductive scribelane structures 1 (para [0023] - “scribe PAD 1”), and the second scribelane portion SP2 being devoid of conductive scribelane structures 1.
Regarding claim 2, Sugiyama teaches the semiconductor substrate a that has a third cut side CS3 and a fourth cut side CS4 opposite to the third cut side CS3, a third scribelane portion SP3 between the third cut side CS3 and the circuit, and a fourth scribelane portion SP4 between the fourth cut side CS4 and the circuit, the third and fourth scribelane portions SP3, SP4 devoid of conductive scribelane structures 1.
Regarding claim 3, Sugiyama teaches the circuit that comprises a sensor circuit portion 3 (para [0028] - “test circuit 3”. A test circuit senses whether or not the circuit being tested is operational or not.) and an interface circuit portion ICP.
Regarding claim 4, a limitation of “configured to operate in an electric field from a high voltage conductor” does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by Sugiyama as it is directed to a capability of the sensor circuit portion. The test circuit 3 of Sugiyama is capable of operating in an electric field from a high voltage conductor, because the image sensor has the same structure as claimed.
Regarding claim 6, Sugiyama teaches the first scribelane portion SP1 that is between a plurality of bond pads (conductive areas of the Test PAD control that is electrically connected to the scribe pads.) and the first cut side CS1.
Regarding independent claim 8, Sugiyama teaches a method of fabricating an integrated circuit (IC), the method comprising:
processing a semiconductor wafer (see Figs. 2A and 2B) in a fabrication flow having a sequence of process stages for creating a plurality of semiconductor dies a, a (see Fig. 3), each containing an instance of the IC (see Fig. 1), the semiconductor wafer providing a substrate for the IC, the processing including forming scribelanes b (see Figs. 2A and 3) extending in a first direction, a first subset SP1 of the scribelanes including conductive scribelane structures 1 and a second subset SP2, SP3 or SP4 of the scribelanes interleaved with the first subset CS1 and being devoid of conductive scribelane structures 1; and
singulating the plurality of semiconductor dies a, a in a dicing operation (para [0026] - “…after the dicing.”).
Regarding claim 9, Sugiyama teaches the scribelanes that are first scribelanes SP1, SP2, and further comprising forming second scribelanes SP3, SP4 extending in a different second direction, wherein the second scribelanes SP3, SP4 are devoid of conductive scribelane structures 1.
Regarding claim 11, Sugiyama teaches a scribelane b devoid of the conductive scribelane structures 1 is formed between first and second adjacent columns Col1, Col2 of the semiconductor dies a, a, the first column Col1 containing semiconductor dies a, a having non-bond-pad sides that face non-bond-pad sides of the semiconductor dies of the second column Col2.
Claim Rejections - 35 USC § 103
Quotation of the statutory basis has been provided above.
Claims 16-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama in view of Tuncer.
Regarding independent claim 16, Sugiyama teaches a semiconductor die a having a first cut side CS1 and an opposite second cut side CS2;
a circuit (see Fig. 3) between the first and second cut sides CS1 and CS2, the circuit including a first circuit portion 3 (para [0028] - “test circuit 3”) and a second circuit portion ISP,
a first scribelane portion SP1 between the circuit and the first cut side CS1 and a second scribelane portion SP2 between the circuit and the second cut side CS2, the first scribelane portion SP1 including conductive scribelane structures 1 (para [0023] - “scribe PAD 1”), and the second scribelane portion SP2 being devoid of conductive scribelane structures 1.
Sugiyama does not teach a package integrated circuit comprising first package leads on a first side of a device package and second package leads on an opposite second side of the device package.
However, Tuncer teaches a package integrated circuit (IC) (see Fig. 2C), comprising:
first package leads 204A-204D (col. 6, ln 23-40 - “terminals 204A-204D and 204E-204H”) on a first side of a device package 200 and second package leads 204E, 204H on an opposite second side of the device package;
a semiconductor die 208 (col. 6, ln 23-40 - “die 208”) having a first cut side and an opposite second cut side;
a circuit (col. 2, ln 29-65) located between the first and second cut sides, the circuit including a first circuit portion and a second circuit portion, the semiconductor die 208 located between the first package leads 204A-204D and the second package leads 204E, 204H;
a lead frame portion 250 (col. 6, ln 1-22 - “conductive pathway 250”) over or a lead frame portion 205 (col. 5, ln 30-61 - “The package 200 includes a die pad 205…”) under the semiconductor die 208, the lead frame portion 250 or 205 extending over the second cut side toward the first cut side and ending over the second circuit portion;
bond pads 218 between the first circuit portion and the first cut side; and
bond wires 252 (col. 5, ln 30-61 - “bond wires 252”) connected between the bond pads 218 and the second package leads 204E, 204H.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the semiconductor device of Sugiyama with the lead frame having die pad and leads as taught by Tuncer so as to implement the semiconductor device in a wire-bonded package (Tuncer, col. 2, ln 29-65) to couple to printed circuit board.
Regarding claim 17, the combination of Sugiyama and Tuncer teaches a current loop in the lead frame portion 250.
Regarding claim 18, the combination of Sugiyama and Tuncer teaches the semiconductor die a that is devoid of bond pads under or over the lead frame portion.
Regarding claim 19, a limitation of “configured to have a DC voltage of at least 300 V with respect to the semiconductor die” does not structurally distinguish the claimed semiconductor device over the semiconductor device taught by the combination of Sugiyama and Tuncer as it is directed to a capability of the lead frame portion. The lead frame portion taught Tuncer of the combination above is capable of having a DC voltage of at least 300 V with respect to the semiconductor die, because it has the same structure as claimed.
Regarding claim 21, Sugiyama of the combination above teaches the semiconductor substrate that has a third cut side CS3 and a fourth cut side CS4 opposite to the third cut side CS3, a third scribelane portion SP3 between the third cut side CS3 and the circuit, and a fourth scribelane portion SP4 between the fourth cut side CS4 and the circuit, the third and fourth scribelane portions SP3, SP4 devoid of conductive scribelane structures 1.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 5 is objected to for depending on a rejected base claim 1 and the intervening claim 3, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 and the intervening claim 3 or the base claim 1 is amended to include all of the limitations of claim 5 and the intervening
claim 3.
Claim 12 is objected to for depending on a rejected base claim 8, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 8 or the base claim 8 is amended to include all of the limitations of claim 12.
Claim 13 is objected to for depending on a rejected base claim 8, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 8 or the base claim 8 is amended to include all of the limitations of claim 13.
Claims 14 and 15 are allowed, because they depend from the allowed claim 13.
Claim 20 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2008/0128690 A1 to Burnside et al.
Pub. No. US 2005/0058006 A1 to Noda
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 20 June 2026
1 The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
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