Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed November 11th, 2025, with respect to the rejections of the independent claims have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection is made in view of Alameldeen et al (US 2022/0206818)..
As Applicant’s arguments are directed toward limitations of the claims added or modified via amendment, they will be addressed in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 4-6, 9, 13-14, 16-17, and 21-28 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al (US 2022/0091581, herein Liu) in view of Alameldeen et al (US 2022/0206818, herein Alameldeen, cited in previous Office Action).
In the following rejections, the device embodiment of claim 9 will be addressed first.
Regarding claim 9, Liu teaches a device comprising:
a fetch circuit configured to fetch instructions from a plurality of blocks of code ([0028], fetch circuit);
a decode circuit ([0028], decode circuit) configured to:
evaluate instructions within a first block of code of the plurality of blocks of code ([0023], [0028], [0030-0031], [0054], load hardening using instruction types or indicators, detected by decoder) to detect whether a conditional move instruction or fence instruction indicating speculative load hardening in the first block of code ([0041], fence uop & [0055], movbr instruction); and
in response to detecting the conditional move instruction or fence instruction indicating speculative load hardening within the first block of code, selectively suppress hardware speculative execution for instructions in the first block of code ([0031], [0035], prevent speculative execution after load hardening indicator found);
evaluate instructions within a second block of code of the plurality of blocks of code to detect that the second block of code does not include a conditional move instruction or fence instruction indicating speculative load hardening ([0028], [0034], decode other instructions besides fence or conditional move);
in response to determining that the second block of code does not indicate speculative load hardening, not suppress hardware speculative execution for the second block of code ([0034], [0054], selective hardening via control/config register setting or hint to indicate loads are not to be hardened);
an execution circuit configured to execute the instructions from the plurality of blocks of code ([0023], execution circuitry).
Liu fails to teach wherein the device is configured to explicitly not suppress hardware speculative execution in response to the second block of code not including the conditional move instruction or fence instruction.
Alameldeen teaches a device configured to evaluate instructions within a block of code and in response to determining that the block of code does not include a conditional move instruction or fence instruction indicating speculative load hardening, not suppress hardware speculative execution for the block of code ([0057-0059], [0061], [0077-0080], allow speculative execution when detecting a load that does not include a bit to indicate speculative hardening).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Liu and Alameldeen to control the load hardening of Liu based on the presence or absence of certain instructions. While Liu does not explicitly state that speculative execution may be allowed for groups of instructions that do not include a load to be hardened, speculative execution is a routine and conventional aspect of the microprocessor art which increases the performance of processors. As both Liu and Alameldeen disclose techniques for performing load, register, and branch hardening for multiple kinds of speculative operations, allowing instructions to execute speculatively when no hardening indicator or instruction type is present would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 13, The combination of Liu and Alameldeen teaches the device of claim 9, wherein the decode circuit is further configured to: store a predicted branch prediction in an address register for an identified conditional branch instruction with the first block of code; and when the decode circuit does not detect a speculative load hardening indicator associated with the identified conditional branch instruction, load the predicted branch condition (Liu [0020], [0055-0056], [0061], conditional branches & branch prediction, [0031], [0038], [0040], nonspeculative branch resolution).
Regarding claim 14, The combination of Liu and Alameldeen teaches the device of claim 9, a schedule circuit configured to hold the predicted branch condition within the address register (Liu [0023], [0056], scheduler circuit).
Regarding claim 16, The combination of Liu and Alameldeen teaches the device of claim 9, further comprising a schedule circuit configured to: suppress hardware speculative execution for instructions in the first block of code (Liu [0031], [0035], prevent speculative execution after load hardening indicator found & [0023], scheduling circuit).
Claims 1, 2, 3, and 8 refer to a method embodiment of the device embodiment of claims 9, 12, 11, and 15, respectively. Therefore, the above rejections for claims 9, 12, 11, and 15, are applicable to claims 1, 2, 3, and 8, respectively.
Regarding claim 4, The combination of Liu and Alameldeen teaches the method of claim 1, wherein the conditional move instruction or fence instruction is detected by a decode circuit within the processor during an instruction decode stage (Liu [0028], [0032], decode circuit to detect hardening conditions).
Regarding claim 5, The combination of Liu and Alameldeen teaches the method of claim 1, wherein the hardware speculative execution is suppressed on a localized basis within the software program (Liu [0053-0054], hints localized to software instruction prefixes).
Regarding claim 6, The combination of Liu and Alameldeen teaches the method of claim 1, wherein the first block of code does not include a conditional move instruction or fence instruction and wherein the method further comprises not suppressing the hardware speculative execution of the first block of code (Liu [0053], disable load hardening mode to execute speculatively, [0054], hints to indicate not to harden loads & Alameldeen [0057-0059], [0061], [0077-0080], allow speculative execution when detecting a load that does not include a bit to indicate speculative hardening).
Regarding claim 21, The combination of Liu and Alameldeen teaches the method of claim 1, wherein the conditional move instruction or fence instruction was inserted into the first block of code by a compiler implementing speculative load hardening (Alameldeen [0060], hardening requirements determined by compiler & Liu [0054], inserting fence uop).
Regarding claim 22, The combination of Liu and Alameldeen teaches the method of claim 1, further comprising detecting, by the processor, a conditional branch instruction within the first block of code prior to evaluating the instructions within the first block of code to detect the conditional move instruction or fence instruction (Liu [0033], branch detection and prediction precedes decoding of load to be hardened).
Regarding claim 23, The combination of Liu and Alameldeen teaches the method of claim 22, wherein evaluating the instructions within the first block of code comprises checking a next flag-consuming instruction following the conditional branch instruction to detect whether the conditional move instruction or fence instruction is present (Liu [0039-0040], detecting consumer uop & Alameldeen [0094], evaluating consumer operation flags).
Regarding claim 24, The combination of Liu and Alameldeen teaches the method of claim 1, wherein evaluating the instructions within the first block of code comprises determining that the conditional move instruction or fence instruction is being utilized for speculative load hardening purposes rather than other purposes (Alameldeen [0057-0059], mode bits to indicate when speculation is disallowed for hardening or other purposes).
Regarding claim 26, The combination of Liu and Alameldeen teaches the method of claim 1, wherein the conditional move instruction or fence instruction is part of the target language code generated by a compiler from source code, wherein the target language code comprises the first block of code (Alameldeen [0060], hardening requirements determined by compiler,m [0256], program language used by compiler & Liu [0054], inserting fence uop).
Claims 17, 27, and 28 refer to a medium embodiment of the method embodiment of claims 1, 21, and 24. Therefore, the above rejections for claims 1, 21, and 24 are applicable to claims 17, 27, and 28.
Claim 25 refers to a device embodiment of the method embodiment of claim 21. Therefore, the above rejection for claim 21 is applicable to claim 25.
3. Claims 7, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liu and Alameldeen in view of Sakalis (US 2021/0365554, herein Sakalis).
Regarding claim 7, Liu and Alameldeen teaches the method of claim 1, further comprising: checking an environment of the first block of code of the processor; and not suppressing the hardware speculative execution of the first block of code (Liu [0053-0054], software interface or hint to allow enabling of disabling of load hardening and speculative execution).
Liu and Alameldeen fails to teach wherein the environment is an enclave.
Sakalis teaches a method comprising checking an environment of a block of code of a processor and not suppressing speculative execution based on the environment being an enclave ([0003-0005], [0049], enclave execution environment allows for secure execution of code).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Liu and Alameldeen with those of Sakalis to control the load hardening of Liu based on the type of execution environment. While Liu does not explicitly contemplate that the load hardening may be disabled based on the processor providing a secure enclave environment for execution, Liu does disclose the use of software hints and flags to enable or disable load hardening. Therefore, allowing these hints or flags to account for the use of a secure execution environment such as an enclave, as disclosed by Sakalis, would expand the degree of control over the speculation mechanisms. As both Liu and Sakalis are directed toward protecting a computing environment from malicious threads, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Claim 10 refers to a device embodiment of the method embodiment of claim 7. Therefore, the above rejection for claim 7 is applicable to claim 10.
Claim 19 refers to a medium embodiment of the method embodiment of claim 7. Therefore, the above rejection for claim 7 is applicable to claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Biernacki (US 2022/0114285) discloses a processor for performing load hardening on conditional move instructions.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183