DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant's election with traverse of Species I: claim 5 (Figs.4a-4b) in the reply filed on 7/20/2026 is acknowledged. The traversal is on the ground(s) that the final product of Species I (Figs. 4a-4b) and the final product of Species II (Figs. 5a-5b) are formed by the same sequence of sub-steps and Species II does not present a large range of species in relation to Species I. The examiner agreed with the Applicant that the funnel shape of connecting element in Species II and the reverse funnel shape of connecting element in Species II can be a design choice. As such, the species are rejoined and claim 5 is examined together with claims 1-4 and 6-12. Claims 1-12 are pending in the application.
Claim Rejections - 35 USC § 112
Claims 7, 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 is rejected for reciting step iii) before step ii) subjected to roughening the exposed portions of the lead terminals. The “exposed” portion means step ii) already performed to expose the terminals as in claim 1; as such step iii) must be after step ii). Corrections in the spec and claim need to be addressed.
Claim 11 is rejected for reciting of the structure including the formation of the connecting element using steps of claim 1. It is not clear which step(s) of claim 1 is/are used to form the connecting element. As best understood, the steps i3-1) and i3-2 are used to form the connecting element and claim 11 is examined as such.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-6, 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20180174951 A1) in view of Reber (US 20120178189 A1)
Regarding claim 1 Fan discloses (Fig. 1) A method (¶ [0017]) for manufacturing a semiconductor package assembly, the method comprising the steps of:
i) forming at least one semiconductor package by steps i1)- i3):
i1) providing a lead frame (112, 114) comprising a first section (112) and a second section (114), the first section being made from a metal material having a first frame side and a second frame side opposite to the first frame side and comprising at least one terminal separated by a gap to the second section, the second section made from the metal material and comprising at least one terminal (Fig. 1);
i2) providing at least one semiconductor die (110) structure having a first die side and a second die side opposite to the first side with the second die side on the first frame side of the first section of the lead frame (Fig. 1);
i3) providing one or more connection elements (120) bridging the gap between the at least one semiconductor die structure on the first section of the lead frame to the at least one terminal of the second section of the lead frame and forming an electrical and mechanical connection (Fig. 1); and
ii) encapsulating the at least one semiconductor die structure, the one or more connection elements and the plurality of terminals with a molding resin (105) leaving at least a portion of at least two terminals exposed, thereby forming at least one encapsulated semiconductor package assembly with terminals at opposite sides (Fig. 1),
Fan is silent regarding wherein the step i3) comprises at least one forming sequence of the substep of: i3-1) providing a layer of a metal powder so that the metal powder is in contact with the at least one semiconductor die structure and one of the at least two terminals of the lead frame; and i3-2) selectively melting with laser light radiation, the layer of the metal powder to form a metal layer.
Reber discloses (Figs. 3-7, ¶¶ [0022-0024]) using selective laser sintering method to form a metal layer (34) on a bond pad (12) by depositing metal powder layer and curing it with a layer beam (30) wherein the shape of the metal layer is controlled by the scanning boundary of the laser beam and the desired thickness is achieved through the iterative applications of metal powder and laser beam scanning.
Artisans in the art would have appreciated a clip connecting a chip to a lead frame terminal would provide a bridge between the chip’s internal circuitry and the external circuitry. In the disclosure of Reber, a pond pad on the surface of an IC or semiconductor die would serve as the physical and electrical interface between the IC or chip’s internal circuitry and its external connections such that the metal layer formed on the bond pad can be realized to bridge the internal circuitry of the die to the external connections of the lead frame terminal. As such the bridge connection can be built on the chip surface and the lead terminal surface to make a bridge connection. Artisans in the art would have appreciated in the additive manufacturing process, the selective laser sintering is a powerful additive process with advantages over traditional 3D printing method; it requires no support structures, yet fully self-supporting because unused powder acts as a natural support for overhangs and complex geometries. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to realize the metal layer formed by the selective laser sintering of Reber to make a bridge connection for the chip of Fan to the external lead. Doing so would streamline the manufacturing process, save the material, and reduce production time.
Regarding claim 2, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Reber further discloses (¶¶ [0022-0024], Figs. 3-7 wherein the forming sequence of the substeps i3-1 and i3-2 is performed multiple times alternately, thereby forming a three-dimensional stack of subsequent melted metal layers.
Regarding claim 5, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Fand and Reber are silent regarding further comprising a surface dimension of a metal layer that has a surface dimension that is larger than the surface dimension of the metal layer formed during the previous forming sequences. While being silent to the surface dimension of a layer is larger than the surface dimension of the metal layer formed during the previous forming sequences, Reber discloses (¶¶ [0022-0024], Figs. 3-7) the powder particle of a layer is uniformly distributed on the layer formed during the previous sequences (Fig. 5), thus by controlling the boundary of the laser to scan a larger dimension than the base layer from previous fused powder, this can be done. Moreover, the un-fused powder of the previous layer would act as a support structure to the current layer such that a larger fused portion on a smaller fused portion is possible. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form metal layer on the chip and the lead to from a connection bridge such that a layer dimension is larger than the layer from previous forming for a diversity of design choices.
Regarding claim 6, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Fan and Reber are silent regarding further comprising a surface dimension of a metal layer that has a surface dimension that is smaller than the surface dimension of the metal layer formed during the previous forming sequences. While being silent to the surface dimension of a layer is smaller than the surface dimension of the metal layer formed during the previous forming sequences, Reber discloses (¶¶ [0022-0024], Figs. 3-7) the powder particle of a layer is uniformly distributed on the layer formed during the previous sequences (Fig. 5), thus by controlling the boundary of the laser to scan a smaller dimension than the base layer from previous fused powder, this can be done. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form metal layer on the chip and the lead to from a connection bridge such that a layer dimension is smaller than the layer from previous forming for a diversity of design choices.
Regarding claim 11, Fan discloses (Fig. 1) A semiconductor package assembly composed of a semiconductor die (110) structure electrically and mechanically attached by one or more connection elements (120) with at least two terminals (ends of 112, 114) and encapsulated by a molding resin (105) so that a portion of the at least two terminals are exposed. Fan is silent regarding wherein the one or more connection elements between the semiconductor die structure and the at least two terminals are formed according to the method steps of claim 1.
In other words, Fan is silent regarding wherein the step i3) comprises at least one forming sequence of the substep of: i3-1) providing a layer of a metal powder so that the metal powder is in contact with the at least one semiconductor die structure and one of the at least two terminals of the lead frame; and i3-2) selectively melting with laser light radiation, the layer of the metal powder to form a metal layer.
Reber discloses (Figs. 3-7, ¶¶ [0022-0024]) using selective laser sintering method to form a metal layer (34) on a bond pad (12) by depositing metal powder layer and curing it with a layer beam (30) wherein the shape of the metal layer is controlled by the scanning boundary of the laser beam and the desired thickness is achieved through the iterative applications of metal powder and laser beam scanning.
Artisans in the art would have appreciated a clip connecting a chip to a lead frame terminal would provide a bridge between the chip’s internal circuitry and the external circuitry. In the disclosure of Reber, a pond pad on the surface of an IC or semiconductor die would serve as the physical and electrical interface between the IC or chip’s internal circuitry and its external connections such that the metal layer formed on the bond pad can be realized to bridge the internal circuitry of the die to the external connections of the lead frame terminal. As such the bridge connection can be built on the chip surface and the lead terminal surface to make a bridge connection. Artisans in the art would have appreciated in the additive manufacturing process, the selective laser sintering is a powerful additive process with advantages over traditional 3D printing method; it requires no support structures, yet fully self-supporting because unused powder acts as a natural support for overhangs and complex geometries. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to realize the metal layer formed by the selective laser sintering of Reber to make a bridge connection for the chip of Fan to the external lead. Doing so would streamline the manufacturing process, save the material, and reduce production time.
Regarding claim 12, Fan discloses A semiconductor package assembly (Fig. 1) composed of a semiconductor die (110) structure electrically and mechanically attached by one or more connection elements with at least two terminals (112, 114) and encapsulated by a molding resin (105) so that a portion (ends of 112, 114) of the at least two terminals are exposed, wherein the one or more connection elements (120) between the semiconductor die structure and the at least two terminals are formed according to the method steps of claim 2.
In other words, Fan is silent regarding wherein the step i3) comprises at least one forming sequence of the substep of: i3-1) providing a layer of a metal powder so that the metal powder is in contact with the at least one semiconductor die structure and one of the at least two terminals of the lead frame; and i3-2) selectively melting with laser light radiation, the layer of the metal powder to form a metal layer and the repetition of steps i3-1 and i3-2 until the desired thickness is achieved.
Reber discloses (Figs. 3-7, ¶¶ [0022-0024]) using selective laser sintering method to form a metal layer (34) on a bond pad (12) by depositing metal powder layer and curing it with a layer beam (30) wherein the shape of the metal layer is controlled by the scanning boundary of the laser beam and the desired thickness is achieved through the iterative applications of metal powder and laser beam scanning.
Artisans in the art would have appreciated a clip connecting a chip to a lead frame terminal would provide a bridge between the chip’s internal circuitry and the external circuitry. In the disclosure of Reber, a pond pad on the surface of an IC or semiconductor die would serve as the physical and electrical interface between the IC or chip’s internal circuitry and its external connections such that the metal layer formed on the bond pad can be realized to bridge the internal circuitry of the die to the external connections of the lead frame terminal. As such the bridge connection can be built on the chip surface and the lead terminal surface to make a bridge connection. Artisans in the art would have appreciated in the additive manufacturing process, the selective laser sintering is a powerful additive process with advantages over traditional 3D printing method; it requires no support structures, yet fully self-supporting because unused powder acts as a natural support for overhangs and complex geometries. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to realize the metal layer formed by the selective laser sintering of Reber to make a bridge connection for the chip of Fan to the external lead. Doing so would streamline the manufacturing process, save the material, and reduce production time.
Claim(s) 3-4, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20180174951 A1) in view of Reber (US 20120178189 A1) and Chaochuang (CN 109676136 B)
Regarding claim 3, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Fan-Reber is silent regarding further comprising controlling a local thickness and/or a local density of each metal layer formed during a forming sequence of the substeps i3-1) and i3- 2) by adjusting at least one manufacturing parameter selected from the group consisting of: a metal powder distribution, a supply velocity of metal powder to be deposited, a metal powder depositing angle relative to a plane formed by the lead frame, a laser light power, a laser light frequency, a laser light wavelength, an ambient process temperature, a metal powder depositing duration time of substep i3-1), and a metal powder melting duration time of substep i3-2).
Chaochuang discloses using selective laser sintering method to form hollow outer structure and to for each single layer powder paving thickness, parameters of scanning speed, scanning distance, and laser power are set respectively (examples shown pg. 13, para. 4-7). Artisans in the art would have appreciated such a relationship laser power, scanning speed and layer thickness are critical to influence the mechanical properties and surface finish. Such it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to match the laser heating and scanning speed profiles to the layer thickness. This coordination would ensure optimal melting and layer cohesion without excessive evaporation or defects.
Regarding claim 4, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Fan and Reber are silent regrading wherein each metal layer formed in substep i3-2) has a thickness of 30- 40 µm.
Chaochuang discloses (pg. 13, para. 5) using selective laser sintering at set parameters to form single layer powder paving thickness between 15µm – 100 µm. Absent unpredictable results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to select a layer thickness between 30-40 µm for the metal powder layer to form the metal layer of Reber to optimize design applications.
Regarding claim 8, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 2. Fan and Reber is silent regarding further comprising controlling a local thickness and/or a local density of each metal layer formed during a forming sequence of the substeps i3-1) and i3- 2) by adjusting at least one manufacturing parameter selected from the group consisting of: a metal powder distribution, a supply velocity of metal powder to be deposited, a metal powder depositing angle relative to a plane formed by the lead frame, a laser light power, a laser light frequency, a laser light wavelength, an ambient process temperature, a metal powder depositing duration time of substep i3-1), and a metal powder melting duration time of substep i3-2).
Chaochuang discloses using selective laser sintering method to form hollow outer structure and to for each single layer powder paving thickness, parameters of scanning speed, scanning distance, and laser power are set respectively (examples shown pg. 13, para. 4-7). Artisans in the art would have appreciated such a relationship laser power, scanning speed and layer thickness are critical to influence the mechanical properties and surface finish. Such it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to match the laser heating and scanning speed profiles to the layer thickness. This coordination would ensure optimal melting and layer cohesion without excessive evaporation or defects.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20180174951 A1) in view of Reber (US 20120178189 A1) and Terai (WO 2014132483 A1)
Regarding claim 7, Fan in view of Reber discloses the method for manufacturing a semiconductor package assembly according to claim 1. Fan – Reber is silent regarding further comprising the step of iii) after a final forming sequence of substeps i3-1) and i3-2) but before step ii), subjecting the exposed portion of the at least two terminals to a surface roughening treatment.
Terai, an analogous art, discloses (Fig. 5-2, pg. 35 last para.) forming roughened portions (18, 19) of the exposed lead frames (1, 5) to prevent corrosion. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to adopt the roughening step as taught by Terai to the modified lead terminals of Fan – Reber to enhance corrosion prevention.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20180174951 A1) in view of Reber (US 20120178189 A1) Terai (WO 2014132483 A1), Wu (CN 215668212 U) and Shibata (JP 2001077223 A)
Regarding claim 9, Fan in view of Reber and Terai disclose the method for manufacturing a semiconductor package assembly according to claim 7. Fan, Reber, and Terai are silent regarding further comprising the step of iv) after step ii) or step iii), wherein step iv) comprises plating the exposed portion of the at least two terminals with a metal plating material.
Su discloses (pag. 7, last para. Under technology field) a surface roughening treatment to be done for an electroless plating of the substrate can enhance adhesive bonding force for subsequent plating layers to attach.
Shibata discloses (pg. 15, third para., Fig. 1) metal plating an external lead terminal (7) can prevent oxidation corrosion of the lead terminals.
Artisans in the art would be motivated by the teaching of Su and Shibata to adopt the metal plating as taught by Shibata to the modified structure of Fan-Reber-Terai such that the roughening surface of the exposed lead frame terminal Fan would be plated with a layer of metal to enhance the bonding of the plated layer to the surface, overall, improving corrosion prevention and delamination.
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to apply a plated metal layer on a roughening surface as taught by Shibata and Su to the modified lead terminal of Fan to enhance the attachment and the corrosion prevention of the lead terminal.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fan (US 20180174951 A1) in view of Reber (US 20120178189 A1) Terai (WO 2014132483 A1), Wu (CN 215668212 U), Shibata (JP 2001077223 A), and Lopez (US 20140210064 A1)
Regarding claim 10, Fan in view of Reber, Terai, Wu, Shibata discloses the method for manufacturing a semiconductor package assembly according to claim 9. But Fan is silent regarding further comprising the step v) after step iv), wherein step v) comprises singulating the encapsulated semiconductor package from the lead frame, thereby forming a single semiconductor package assembly.
Lopez discloses (Fig. 1, ¶ [0032]) an individual chip unit (Fig. 1) where the lead frame (10) is part of a leadframe strip having multiple intergrally connected leadframes and the distal ends of the lead portions 34, 36, 38, 42 are connected to other portions of this leadframe strip which holds these lead portions in the relationship shown in FIG. 1 until after molding and singulation. Thus, all the elements of the package including the distal portions of the leadframe, the chip, and the connecting elements are held together in the molding compound and then singulated to form individual package.
Artisans in the art would have appreciated multiple chip units are designed on a single leadframe strip and then encapsulated and singulated to form individual package. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have multiple modified package units of Fan designed on a single leadframe strip and encapsulate and singulate them into individual packages. Doing so would streamline production processes and avoid wasting material.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Talledo (EP 4415042 A2) and Shi (US 20080087992 A1) disclose a package with a lead frame, a chip, and a clip connecting the chip to the lead terminal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T HOANG whose telephone number is (571)272-5622. The examiner can normally be reached M-F 8:00 - 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DTH/
Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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