DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 6-7, and 9-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ryu et al. (U.S. Patent No. 11,825,643).
Regarding to claim 1, Ryu teaches a semiconductor memory device comprising:
a substrate (Figs. 1A-C, element LS);
a structure including a plurality of word lines (Figs. 1A-C, elements WL) and a plurality of interlayer insulating films (Figs. 1A-C, elements LSPT), wherein the plurality of word lines and the plurality of interlayer insulating films are alternately stacked on the substrate (Figs. 1A-C);
a channel region disposed between two adjacent word lines of the plurality of word lines in a vertical direction (Figs. 1A-C, elements CH);
a first source/drain region disposed on a first side of the channel region (Figs. 1A-C, elements SD1);
a second source/drain region disposed on a second side of the channel region (Figs. 1A-C, elements SD2);
a bit line which extends in the vertical direction on the substrate, wherein the bit line is connected to the first source/drain region (Figs. 1A-C, element BL);
a capping insulating film disposed between the bit line and the plurality of word lines (Figs. 1A-C, element CPL; column 8, line 14); and
a data storage connected to the second source/drain region (Figs. 1A-C, element CAP; column 6, lines 25-28),
wherein at least a part of the first source/drain region protrudes from a sidewall of the capping insulating film toward the bit line (Fig. 1C, first source/drain region SD1 protrudes from a sidewall of the capping insulating film CPL toward the bit line BL).
Regarding to claim 6, Ryu teaches a sidewall of the first source/drain region adjacent to the bit line includes a first extending part, a second extending part opposite to the first extending part, and a connecting part that connects the first extending part and the second extending part (Fig. 1C, sidewall of the first source/drain region adjacent to the bit line is arbitrary divided into three parts, a first extending part, a second extending part opposite to the first extending part, and a connecting part that connects the first extending part and the second extending part).
Regarding to claim 7, Ryu teaches the connecting part extends in the vertical direction (Fig. 1C).
Regarding to claim 9, Ryu teaches at least a part of the first source/drain region is in contact with the capping insulating film (Fig. 1C).
Regarding to claim 10, Ryu teaches at a boundary between the first source/drain region and the channel region, the first source/drain region or the channel region includes oxygen (0), fluorine (F), chlorine (Cl), or bromine (Br) (column 5, lines 42-45).
Regarding to claim 11, Ryu teaches a silicide film disposed between the first source/drain region and the bit line (column 4, lines 40-41).
Regarding to claim 12, Ryu teaches
a gate insulating film disposed between the plurality of word lines and the channel region (Fig. 1C, element GD; column 4, line 51),
wherein at least a part of the gate insulating film overlaps the first source/drain region in a horizontal direction intersecting the vertical direction (Fig. 1C).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643), as applied to claim 1 above, in view of Kim (U.S. Patent No. 11,910,590).
Regarding to claim 2, Ryu does not disclose at a boundary between the first source/drain region and the channel region, the channel region has a first width and the first source/drain region has a second width in the vertical direction, and wherein the first width is smaller than the second width. Kim discloses at a boundary between the first source/drain region and the channel region, the channel region has a first width and the first source/drain region has a second width in the vertical direction, and wherein the first width is smaller than the second width (Fig. 2C, Fig. 8D). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu in view of Kim to configure at a boundary between the first source/drain region and the channel region, the channel region having a first width and the first source/drain region having a second width in the vertical direction, the first width is smaller than the second width, in order to increase switching speed.
Regarding to claim 4, Ryu teaches the first source/drain region includes a first region disposed in the bit line and a second region between the first region and the channel region (Fig. 1C). Ryu does not disclose a width of the first region in the vertical direction increases and then decreases in a direction away from the channel region. Kim discloses a width of the first region in the vertical direction increases in a direction away from the channel region (Fig. 2C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu in view of Kim to configure a width of the first region in the vertical direction increasing in a direction away from the channel region in order to increase contact area between the bit lines and the S/D region. Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Ryu and Kim to configure a width of the first region in the vertical direction increasing and then decreasing in a direction away from the channel region in order to further increase contact area, thus to increase reliability.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643), as applied to claim 1 above, in view of Khaderbad et al. (U.S. Patent No. 12,266,709).
Regarding to claim 3, Ryu is silent as to the material of the first source/drain region. Khaderbad discloses a first source/drain region includes SiP or SiAs (column 5, lines 51-53). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu in view of Khaderbad to include SiP or SiAs in the first source/drain region in order to obtained desired performance. Furthermore, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to include SiP or SiAs in the first source/drain region, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643), as applied to claim 1 above.
Regarding to claim 5, Ryu does not disclose a sidewall of the first source/drain region adjacent to the bit line includes a tip part. However, it would have been an obvious matter of design choice to include a tip part in a sidewall of the first source/drain region adjacent to the bit line, since applicant has not disclosed that the tip part solves any stated problem or is for any particular purpose and it appears that the invention would perform equally well without a tip part.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643), as applied to claims 1 and 6-7 above.
Regarding to claim 8, Ryu does not disclose the connecting part is concave with respect to the channel region. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the connecting part to be concave with respect to the channel region, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claims 13-14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643) in view of Kim (U.S. Patent No. 11,910,590).
Regarding to claim 13, Ryu teaches a semiconductor memory device comprising:
a substrate (Figs. 1A-C, element LS);
a structure including a plurality of word lines (Figs. 1A-C, elements WL) and a plurality of interlayer insulating films (Figs. 1A-C, elements LSPT), wherein the plurality of word lines and the plurality of interlayer insulating films are alternately stacked on the substrate (Figs. 1A-C);
a channel region disposed between two adjacent word lines of the plurality of word lines in a vertical direction (Figs. 1A-C, elements CH);
a bit line which extends in the vertical direction on the substrate (Figs. 1A-C, element BL);
a plurality of capping insulating films disposed between the bit line and the plurality of word lines (Figs. 1A-C, elements CPL; column 8, line 14);
a first source/drain region which is disposed between the bit line and the channel region and between two adjacent capping insulating films of the plurality of capping insulating films in the vertical direction, wherein the first source/drain region at least partially overlaps the bit line in the vertical direction (Figs. 1A-C, elements SD1, first source/drain region overlaps the bit line in the vertical direction at the interface region);
a second source/drain region opposite to the first source/drain region, wherein the channel region is disposed between the first source/drain region and the second source/drain region (Figs. 1A-C, elements SD2); and
a data storage connected to the second source/drain region (Figs. 1A-C, element CAP; column 6, lines 25-28),
wherein the first source/drain region includes a first region overlapping the bit line in the vertical direction and a second region between the first region and the channel region (Fig. 1C, the first region is the interface region, the second region is the main body of the first source/drain region).
Ryu does not disclose a width of the first region in the vertical direction increases and then decreases in a direction away from the channel region.
Kim discloses a width of the first region in the vertical direction increases in a direction away from the channel region (Fig. 2C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu in view of Kim to configure a width of the first region in the vertical direction increasing in a direction away from the channel region in order to increase contact area between the bit lines and the S/D region.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Ryu and Kim to configure a width of the first region in the vertical direction increasing and then decreasing in a direction away from the channel region in order to further increase contact area, thus to increase reliability.
Regarding to claim 14, Ryu teaches a silicide film disposed between the first source/drain region and the bit line (column 4, lines 40-41).
Regarding to claim 16, Ryu teaches the data storage includes a storage electrode connected to the second source/drain region (Fig. 1C, element SN), a plate electrode on the storage electrode (Fig. 1C, element PL), and a capacitor dielectric film between the storage electrode and the plate electrode (Fig. 1C, element DE).
Regarding to claim 17, Ryu teaches at least a part of the first source/drain region is in contact with the plurality of capping insulating films (Fig. 1C).
Regarding to claim 18, Ryu teaches at a boundary between the first source/drain region and the channel region, the first source/drain region or the channel region includes oxygen (0), fluorine (F), chlorine (Cl), or bromine (Br) (column 5, lines 42-45).
Regarding to claim 19, Ryu teaches a structure of a crystal grain of the first source/drain region is different from a structure of a crystal grain of the channel region (Fig.1C, the first source/drain region is doped while the channel region is undoped, thus structure of a crystal grain of the first source/drain region is different from structure of a crystal grain of the channel region).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (U.S. Patent No. 11,825,643), as applied to claim 13 above, in view of Kim (U.S. Patent No. 11,910,590).
Regarding to claim 15, Ryu does not disclose at a boundary between the first source/drain region and the channel region, the channel region has a first width and the first source/drain region has a second width in the vertical direction, and wherein the first width is less than the second width. Kim discloses at a boundary between the first source/drain region and the channel region, the channel region has a first width and the first source/drain region has a second width in the vertical direction, and wherein the first width is smaller than the second width (Fig. 8D). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ryu in view of Kim to configure at a boundary between the first source/drain region and the channel region, the channel region having a first width and the first source/drain region having a second width in the vertical direction, the first width is smaller than the second width, in order to increase switching speed.
Allowable Subject Matter
Claim 20 is allowed. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 20, the prior art fails to anticipate or render obvious the combination of limitations including “the first region protrudes from a plurality of sidewalls of the plurality of capping insulating films and overlaps the bit line in the vertical direction, and the second region is between the first region and the channel region, wherein a sidewall of the first source/drain region include a first extending part and a second extending part opposite to the first extending part, wherein a distance in the vertical direction from the first extending part to the second extending part increases and then decreases in a direction away from the channel region”.
Comparing to the prior-art of the record, the most relevant prior art is Ryu et al. (U.S. Patent No. 11,825,643). Ryu discloses the limitation of claim 20 except for the limitations listed above.
Ryu teaches a semiconductor memory device comprising:
a substrate (Figs. 1A-C, element LS);
a structure including a plurality of word lines (Figs. 1A-C, elements WL) and a plurality of interlayer insulating films (Figs. 1A-C, elements LSPT), wherein the plurality of word lines and the plurality of interlayer insulating films are alternately stacked on the substrate (Figs. 1A-C);
a channel region disposed between two adjacent word lines of the plurality of word lines in a vertical direction (Figs. 1A-C, elements CH);
a first source/drain region disposed on a first side of the channel region (Figs. 1A-C, elements SD1);
a second source/drain region disposed on a second side of the channel region (Figs. 1A-C, elements SD2);
a bit line which extends in the vertical direction on the substrate, wherein the bit line is connected to the first source/drain region (Figs. 1A-C, element BL);
a silicide film disposed between the first source/drain region and the bit line (column 4, lines 40-41);
a plurality of capping insulating films disposed between the bit line and the plurality of word lines (Figs. 1A-C, elements CPL; column 8, line 14);
a data storage connected to the second source/drain region (Figs. 1A-C, element CAP; column 6, lines 25-28),
wherein the data storage includes a storage electrode connected to the second source/drain region (Fig. 1C, element SN), a plate electrode on the storage electrode (Fig. 1C, element PL), and a capacitor dielectric film between the storage electrode and the plate electrode (Fig. 1C, element DE),
wherein the first source/drain region includes a first region and a second region (Fig. 1C);
wherein at a boundary between the first source/drain region and the channel region, the first source/drain region or the channel region includes oxygen (0), fluorine (F), chlorine (Cl), or bromine (Br) (column 5, lines 42-45).
Pertinent Art
For the benefits of the Applicant, US-11729962-B2, US-11563005-B2, US-12369306-B2, US-11950404-B2, US-11844206-B2, US-11910591-B2, US-11864374-B2, and US-12010829-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose “the first region protrudes from a plurality of sidewalls of the plurality of capping insulating films and overlaps the bit line in the vertical direction, and the second region is between the first region and the channel region, wherein a sidewall of the first source/drain region include a first extending part and a second extending part opposite to the first extending part.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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