DETAILED ACTION
This action is responsive to the application No. 18/620,416 filed on March 28, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I and Modifications B and X, corresponding to claims 1-3, 5, 7, 9-16, 19, and 20, in the reply filed on June 25, 2026, is acknowledged. Claims 4, 6, 8, 17, and 18 are withdrawn from consideration.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7, 9-14 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2020/0365558).
(Re Claim 1) Lee teaches a semiconductor package, comprising (see Fig. 15 and supporting text):
a first redistribution substrate (132);
a first semiconductor chip (120) on a top surface of the first redistribution substrate, wherein the first semiconductor chip comprises a plurality of first pads (120) on a top surface of the first semiconductor chip;
a second redistribution substrate (142+162) on the top surface of the first semiconductor chip;
a first vertical connection structure (110) adjacent one side of the first semiconductor chip, wherein the first redistribution substrate and the second redistribution substrate are electrically connected to each other by the first vertical connection structure (as shown);
a second semiconductor chip (181) on a top surface of the second redistribution substrate;
a first molding layer (191) on the second semiconductor chip;
a third redistribution substrate (159’/132’ or 210 or 159’/132’+210) on a top surface of the first molding layer; and
a second vertical connection structure (170) on the top surface of the second redistribution substrate and adjacent one side of the second semiconductor chip,
wherein the second redistribution substrate and the third redistribution substrate are electrically connected to each other by the second vertical connection structure (as shown),
wherein a wiring pattern of the second redistribution substrate is coupled to the plurality of first pads of the first semiconductor chip (as shown).
(Re Claim 5) wherein a bottom surface of the first semiconductor chip is in direct contact with the top surface of the first redistribution substrate (where pad contacts wiring), and a wiring pattern (133) of the first redistribution substrate is directly coupled to a plurality of second pads (123) on the bottom surface of the first semiconductor chip (Fig. 15).
(Re Claim 7) wherein the second vertical connection structure (170) comprises a second connection substrate (171a+171b+173a+173b) that connects the second redistribution substrate to the third redistribution substrate, the second connection substrate has a second opening (170H) in the second connection substrate, the second semiconductor chip is in the second opening, and the first molding layer is in a space between the second connection substrate and the second semiconductor chip (Fig. 15).
(Re Claim 9) wherein the first semiconductor chip further comprises: a plurality of first through vias (125) that penetrate the first semiconductor chip and are exposed on a bottom surface of the first semiconductor chip; and a plurality of second pads (123) on the bottom surface of the first semiconductor chip, wherein a wiring pattern of the first redistribution substrate is coupled through the plurality of second pads to the plurality of first through vias (Fig. 15).
(Re Claim 10) wherein the second semiconductor chip further comprises: a plurality of second through vias (185) that penetrate the second semiconductor chip and that are exposed on a top surface of the second semiconductor chip; and a plurality of third pads (183) on the top surface of the second semiconductor chip, wherein a wiring pattern of the third redistribution substrate is coupled through the plurality of third pads to the plurality of second through vias (Fig. 15).
(Re Claim 11) further comprising a plurality of second connection terminals (182) between the second semiconductor chip and the second redistribution substrate, wherein the second semiconductor chip is connected to the second redistribution substrate by the plurality of second connection terminals (Fig. 15).
(Re Claim 12) wherein the first semiconductor chip is arranged such that an active surface (surface with pads, facing upward) of the first semiconductor chip faces a bottom surface of the third redistribution substrate, and the second semiconductor chip is arranged such that an active surface (surface with pads, facing downward) of the second semiconductor chip faces the top surface of the first redistribution substrate (Fig. 15).
(Re Claim 13) wherein a width of the second semiconductor chip is greater than a width of the first semiconductor chip (Fig. 15).
(Re Claim 14) further comprising an upper package (P3) on a top surface of the third redistribution substrate.
(Re Claim 19) Lee teaches a semiconductor package, comprising (see Fig. 15 and supporting text):
a lower package (P1+P2); and
an upper package (P3) on the lower package,
wherein the lower package comprises:
a first redistribution substrate (132);
a first connection substrate (110) on a top surface of the first redistribution substrate, wherein the first connection substrate comprises a first opening (110H) in the first connection substrate;
a first semiconductor chip (121) in the first opening and on the top surface of the first redistribution substrate, wherein the first semiconductor chip comprises a plurality of first pads (122) on a top surface of the first semiconductor chip;
a plurality of external terminals (193) on a bottom surface of the first redistribution substrate;
a second redistribution substrate (142/162) on the first connection substrate and the first semiconductor chip;
a second connection substrate (170) on a top surface of the second redistribution substrate, wherein the second connection substrate comprises a second opening (170H) in the second connection substrate;
a second semiconductor chip (181) in the second opening and on the top surface of the second redistribution substrate; and
a third redistribution substrate (132’/159’) on the second redistribution substrate,
wherein the upper package comprises: an upper package substrate (210); and
an upper package chip (220A) on the upper package substrate,
wherein a wiring pattern of the second redistribution substrate is coupled to the plurality of first pads of the first semiconductor chip (Fig. 15).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 15, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2020/0365558) in view of Kim et al. (US 2020/0335469).
(Re Claim 2) further comprising a second molding layer (130) on the first semiconductor chip.
Lee is silent regarding a wiring pattern of the second redistribution substrate penetrates the first molding layer and is coupled to the plurality of first pads. A PHOSITA desiring to make, use, and improve upon Lee’s package structure would be motivated to look to related art to teach possible modifications to determine if these offer any advantages. Related art from Kim similarly teaches a package structure and teaches several art recognized structural alternatives for the first and second RDLs, first chip, molding layer, and wiring. Kim’s arrangement in Fig. 11 is analogous to Lee’s Fig. 15 wherein the first chip 120 is in contact with the second RDL 140 and the wiring from the first RDL penetrates the molding layer 130 to contact the chip. Kim’s alternative arrangements in Figs. 10 and 13 shows the first chip in contact with the first RDL, surrounded by molding layer 130 and the second RDL comprises protruding wiring that penetrates the molding layer to contact the chip. These two alternative structures are a result of whether the first chip is assembled and molded by starting with the first chip disposed on the first RDL followed by molding and then forming the second RDL, or if the first chip is disposed on the second RDL followed by molding and then forming the first RDL. Each results in a functional package structure comprising the chip encapsulated in the molding, the two RDLs, and the necessary connections, each alternative obvious to try, and having a clear expectation of success, also see KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). In view of Kim, a PHOSITA would find it obvious to try the art recognized alternative of disposing the first chip directly on the first RDL, then molding, then forming the second RDL over the first chip and molding layer, thereby forming the penetrating wiring pattern pf the second RDL from the top of the first chip to contact the pads through the molding layer in Lee. This alternative sequence is advantageous as this allows for separate testing of the first RDL and subsequently the combination of first RDL with the first chip, prior to forming the second RDL thereby improving yields and reducing rework.
(Re Claim 3) wherein the first vertical connection structure (110) comprises a first connection substrate (111b+113b+111a+113a) that connects the first redistribution substrate to the second redistribution substrate, the first connection substrate has a first opening (110H) in the first connection substrate, the first semiconductor chip is in the first opening, and the second molding layer is in a space between the first connection substrate and the first semiconductor chip (Fig. 15).
(Re Claim 15) Lee teaches a semiconductor package, comprising (see Fig. 15 and corresponding text):
a first redistribution substrate (132);
a second redistribution substrate (142 or 162 or 142+162) on the first redistribution substrate;
a first connection substrate (110) between the first redistribution substrate and the second redistribution substrate, wherein the first connection substrate comprises a first opening (110H) in the first connection substrate and a plurality of first pads (112a) on a top surface of the first connection substrate;
a first semiconductor chip (121) in the first opening between the first redistribution substrate and the second redistribution substrate, wherein the first semiconductor chip comprises a plurality of first through vias (125) that penetrate the first semiconductor chip;
a first molding layer (130) between the first redistribution substrate and the second redistribution substrate, wherein the first molding layer is on the first semiconductor chip and the first connection substrate and is in a space between the first semiconductor chip and the first connection substrate (as shown);
a third redistribution substrate (159’/132’ or 210 or 159’/132’+210) on the second redistribution substrate;
a second connection substrate (170 or 170 sans 172a) between the second redistribution substrate and the third redistribution substrate, wherein the second connection substrate comprises a second opening (170H) in the second connection substrate and a plurality of second pads (172c) on a top surface of the second connection substrate; and
a second semiconductor chip (181) in the second opening between the second redistribution substrate and the third redistribution substrate, wherein the second semiconductor chip and the second connection substrate are connected to a top surface of the second redistribution substrate by a plurality of first connection terminals (multiple interpretations: (1) if second RDL includes 162 then terminals are 182 and 172a, (2) if second RDL is 142, then terminals may be 182/172a or these may be 195, unlabeled, refer to Fig. 9) between the second semiconductor chip and the second redistribution substrate and between the second connection substrate and the second redistribution substrate.
Lee is silent regarding a wiring pattern of the second redistribution substrate penetrates the first molding layer and is coupled to the plurality of first pads. A PHOSITA desiring to make, use, and improve upon Lee’s package structure would be motivated to look to related art to teach possible modifications to determine if these offer any advantages. Related art from Kim similarly teaches a package structure and teaches several art recognized structural alternatives for the first and second RDLs, first chip, molding layer, and wiring. Kim’s arrangement in Fig. 11 is analogous to Lee’s Fig. 15 wherein the first chip 120 is in contact with the second RDL 140 and the wiring from the first RDL penetrates the molding layer 130 to contact the chip. Kim’s alternative arrangements in Figs. 10 and 13 shows the first chip in contact with the first RDL, surrounded by molding layer 130 and the second RDL comprises protruding wiring that penetrates the molding layer to contact the chip. These two alternative structures are a result of whether the first chip is assembled and molded by starting with the first chip disposed on the first RDL followed by molding and then forming the second RDL, or if the first chip is disposed on the second RDL followed by molding and then forming the first RDL. Each results in a functional package structure comprising the chip encapsulated in the molding, the two RDLs, and the necessary connections, each alternative obvious to try, and having a clear expectation of success, also see KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). In view of Kim, a PHOSITA would find it obvious to try the art recognized alternative of disposing the first chip directly on the first RDL, then molding, then forming the second RDL over the first chip and molding layer, thereby forming the penetrating wiring pattern pf the second RDL from the top of the first chip to contact the pads through the molding layer in Lee. This alternative sequence is advantageous as this allows for separate testing of the first RDL and subsequently the combination of first RDL with the first chip, prior to forming the second RDL thereby improving yields and reducing rework.
(Re Claim 16) further comprising a second molding layer (191) on the second redistribution substrate, wherein the second molding layer is on the second semiconductor chip and the second connection substrate and is in a space between the second semiconductor chip and the second connection substrate (Fig. 15), wherein a wiring pattern (132’) of the third redistribution substrate penetrates the second molding layer (191) and is coupled to the plurality of second pads (172c).
(Re Claim 20) further comprising: a first molding layer (130) between the first redistribution substrate and the second redistribution substrate, wherein the first molding layer is on the first semiconductor chip and the first connection substrate and is in a space between the first semiconductor chip and the first connection substrate (as shown); and
a second molding layer (191) between the second redistribution substrate and the third redistribution substrate, wherein the second molding layer is on the second semiconductor chip and the second connection substrate and is in a space between the second semiconductor chip and the second connection substrate (as shown).
Lee is silent regarding the wiring pattern of the second redistribution substrate penetrates the first molding layer to connect the first connection substrate to the first semiconductor chip. A PHOSITA desiring to make, use, and improve upon Lee’s package structure would be motivated to look to related art to teach possible modifications to determine if these offer any advantages. Related art from Kim similarly teaches a package structure and teaches several art recognized structural alternatives for the first and second RDLs, first chip, molding layer, and wiring. Kim’s arrangement in Fig. 11 is analogous to Lee’s Fig. 15 wherein the first chip 120 is in contact with the second RDL 140 and the wiring from the first RDL penetrates the molding layer 130 to contact the chip. Kim’s alternative arrangements in Figs. 10 and 13 shows the first chip in contact with the first RDL, surrounded by molding layer 130 and the second RDL comprises protruding wiring that penetrates the molding layer to contact the chip. These two alternative structures are a result of whether the first chip is assembled and molded by starting with the first chip disposed on the first RDL followed by molding and then forming the second RDL, or if the first chip is disposed on the second RDL followed by molding and then forming the first RDL. Each results in a functional package structure comprising the chip encapsulated in the molding, the two RDLs, and the necessary connections, each alternative obvious to try, and having a clear expectation of success, also see KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007). In view of Kim, a PHOSITA would find it obvious to try the art recognized alternative of disposing the first chip directly on the first RDL, then molding, then forming the second RDL over the first chip and molding layer, thereby forming the penetrating wiring pattern pf the second RDL from the top of the first chip to contact the pads through the molding layer in Lee. This alternative sequence is advantageous as this allows for separate testing of the first RDL and subsequently the combination of first RDL with the first chip, prior to forming the second RDL thereby improving yields and reducing rework.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related packages with RDLs, chips, molding layers, TSVs, pads, and connection structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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