DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-13 and 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dutta et al. (11,462,583).
Re claim 1, Dutta et al. disclose (Fig. 8) a substrate (104) including a cell region (124) and a peripheral region (122/125); a first lower insulating layer (110) on the cell region (124) and extending onto the peripheral region (122/125); a second lower insulating layer (126) on the cell region and on the first lower insulating layer and extending onto the first lower insulating layer on the peripheral region; data storage patterns (304) on the second lower insulating layer on the cell region; a cell insulating layer (310) on the cell region and on the second lower insulating layer and covering the data storage patterns; and a peripheral insulating layer (402) on the peripheral region and on the second lower insulating layer and including a material different from materials of the cell insulating layer (Col. 8, lines 30-35 & 60-61), wherein a thickness of the second lower insulating layer (126) on the peripheral region is smaller than a maximum thickness of the second lower insulating layer on the cell region (Col. 8, lines 26-29).
Re claim 2, Dutta et al. disclose wherein an upper surface of the second lower insulating layer (126) on the peripheral region (122/125) is at a lower height than an uppermost surface of the second lower insulating layer on the cell region (124).
Re claim 5, Dutta et al. disclose wherein the peripheral insulating layer (402) is in contact with the upper surface of the second lower insulating layer (126) on the peripheral region (122/125).
Re claim 6, Dutta et al. disclose wherein the peripheral insulating layer includes an insulating material having a lower dielectric constant than that of the cell insulating layer (Col. 8, lines 30-35 & 60-21).
Re claim 7, Dutta et al. disclose further comprising: an upper insulating layer (502) on the cell insulating layer (310), wherein the peripheral insulating layer (402) is in contact with a side surface of the cell insulating layer (310) and a side surface of the upper insulating layer (502).
Re claim 8, Dutta et al. disclose wherein the peripheral insulating layer (402) includes an insulating material having a lower dielectric constant than that of the cell insulating layer (310) and the upper insulating layer (Col. 8, lines 30-35 & 60-21).
Re claim 9, Dutta et al. disclose wherein the second lower insulating layer (126~ SiCN:H, SiC SiN) includes a material different from materials of the first lower insulating layer (110~ low k).
Re claim 10, Dutta et al. disclose further comprising: a peripheral conductive contact (114/404/406) on the peripheral region, penetrating the first lower insulating layer and the second lower insulating layer and penetrating a lower portion of the peripheral insulating layer, wherein the peripheral conductive contact includes a first portion (114) in the first lower insulating layer, a second portion (404) in the second lower insulating layer, and a third portion (406) in the peripheral insulating layer, and a width of the first portion (114) is smaller than a width of the third portion (406).
Re claim 11, Dutta et al. disclose wherein a width of the second portion (404) decreases as the second portion approaches the first portion (114).
Re claim 12, Dutta et al. disclose further comprising: lower electrode contacts (128/120) on the cell region, penetrating the first lower insulating layer (110) and the second lower insulating layer (126), and connected to the data storage patterns (304), respectively; and wiring lines (112) between the substrate and the first lower insulating layer, wherein the lower electrode contacts and the peripheral conductive contact penetrate the first lower insulating layer and are connected to the wiring lines (Col. 5, lines 18-38).
Re claim 13, Dutta et al. disclose a substrate including a cell region (124) and a peripheral region (122/125); a first lower insulating layer (110) on the cell region and extending onto the peripheral region; a second lower insulating layer (126) on the cell region and on the first lower insulating layer and extending onto the first lower insulating layer on the peripheral region; data storage patterns (304) on the second lower insulating layer on the cell region; lower electrode contacts (128/120) on the cell region, penetrating the first lower insulating layer and the second lower insulating layer, and connected to the data storage patterns, respectively; a cell insulating layer (310) on the second lower insulating layer on the cell region and covering the data storage patterns; a peripheral insulating layer (402) on the peripheral region and on the second lower insulating layer and including a material different from materials of the cell insulating layer; and a peripheral conductive contact (114/404/406) in the peripheral insulating layer and penetrating the first lower insulating layer and the second lower insulating layer on the peripheral region, wherein an upper surface of the second lower insulating layer on the peripheral region is at a lower height than an uppermost surface of the second lower insulating layer on the cell region (Fig. 8), and the peripheral insulating layer (402) is in contact with a side surface of the cell insulating layer and the upper surface of the second lower insulating layer on the peripheral region.
Re claim 16, Dutta et al. disclose further comprising: an upper insulating layer (502) on the cell insulating layer (310), wherein the peripheral insulating layer (402) is in contact with a side surface of the cell insulating layer (310) and a side surface of the upper insulating layer (502).
Re claim 17, Dutta et al. disclose wherein the peripheral insulating layer (402) includes an insulating material having a lower dielectric constant than that of the cell insulating layer (310) and the upper insulating layer (Col. 8, lines 30-35 & 60-21).
Re claim 18, Dutta et al. disclose wherein the first lower insulating layer (110~ low k) and the second lower insulating layer (126~ SiCN:H, SiC SiN) include different materials.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 4, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. as applied to claims 1, 2, 5-13 and 16-18 above, and further in view of Peng et al. (2020/0106007) and Dutta et al. (2021/0305494).
Re claims 3 and 14, Dutta et al. does not disclose wherein the second lower insulating layer on the cell region has a recessed upper surface that is recessed toward the substrate and is between the data storage patterns, and the recessed upper surface of the second lower insulating layer on the cell region is at a lower height than the uppermost surface of the second lower insulating layer on the cell region.
Peng et al. disclose wherein the second lower insulating layer on the cell region has a recessed upper surface that is recessed toward the substrate (Fig. 2 ~ surface layer 140’) and is between the data storage patterns (180/182), and the recessed upper surface of the second lower insulating layer on the cell region is at a lower height than the uppermost surface of the second lower insulating layer on the cell region (Fig. 2).
It would have been obvious to one of ordinary skill in the art to combine Dutta et al. and Peng et al. to enable the recessed insulating layer of Peng et al. to be used in the device of Dutta et al. to reduce parasitic capacitance, improve photolithography alignment and provide reliable electrical isolation.
Re claim 4, Peng et al. disclose further comprising: lower electrode contacts (150) on the cell region (CR) and in the second lower insulating layer (140’) and respectively connected to the data storage patterns (180/182), wherein the data storage patterns are on the lower electrode contacts (150), respectively, and wherein the uppermost surface of the second lower insulating layer (140’) on the cell region (CR) is at a same height as upper surfaces of the lower electrode contacts (150) (Fig. 2).
Re claim 15, the combination of Dutta et al. and Peng et al. does not disclose further comprising: a capping insulating layer interposed between a side surface of each of the data storage patterns and the cell insulating layer, and extending between the recessed upper surface of the second lower insulating layer on the cell region and the cell insulating layer, wherein the peripheral insulating layer is in contact with a side surface of the capping insulating layer.
Dutta et al. (‘494) disclose further comprising: a capping insulating layer (138) interposed between a side surface of each of the data storage patterns (132) and the cell insulating layer (140).
The combination would disclose the capping insulating layer extending between the recessed upper surface of the second lower insulating layer on the cell region and the cell insulating layer, wherein the peripheral insulating layer is in contact with a side surface of the capping insulating layer in Fig. 8 of Dutta et al. (11,462,583).
It would have been obvious to one of ordinary skill in the art to combine Dutta et al., Peng et al. and Dutta et al. (494) to enable capping insulating layer of Dutta et al. (‘494) to be used in the device of the combination to protect the memory pillar (e.g., the memory stack 132) from conductive material that will be formed during subsequent processing ([0057]).
Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. as applied to claims 1, 2, 5-13 and 16-18 above, and further in view of the following comments.
Re claims 19 and 20, Dutta et al. disclose wherein the peripheral conductive contact includes a first portion (114) in the first lower insulating layer, a second portion (404) in the second lower insulating layer, and a third portion (406) in the peripheral insulating layer (Fig. 8).
Dutta et al. does not clearly disclose a side surface of the first portion is inclined at a first angle with respect to a lower surface of the first lower insulating layer, a side surface of the second portion is inclined at a second angle with respect to a lower surface of the second lower insulating layer, and the second angle is different from the first angle; wherein a side surface of the third portion is inclined at a third angle with respect to the upper surface of the second lower insulating layer on the peripheral region, and the second angle is different from the third angle.
It would have been obvious to one of ordinary skill in the art to include a side surface of the first portion is inclined at a first angle with respect to a lower surface of the first lower insulating layer, a side surface of the second portion is inclined at a second angle with respect to a lower surface of the second lower insulating layer, and the second angle is different from the first angle, and a side surface of the third portion is inclined at a third angle with respect to the upper surface of the second lower insulating layer on the peripheral region, and the second angle is different from the third angle since it is well known in the art that interconnects/contacts with inclined (sloped) sidewalls rather than strictly vertical ones improves structural stability, prevents void formation during metal filling, and lowers overall electrical resistance.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include inclined sides with angles to the contacts in Dutta et al. to improve structural stability, prevent void formation during metal filling, and lowers overall electrical resistance.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 12,063,875 B2, US 2024/0081083 A1 disclose a similar configuration for a memory device with data storage patterns.
Conclusion
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/MICHELLE MANDALA/Primary Examiner, Art Unit 2893 June 23, 2026
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