CTNF 18/620,542 CTNF 101872 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on March 28, 2024 is in compliance with time for filing requirements of 3 7 C.F.R. 1.97, and thus, the information disclosure statement has been considered except as otherwise indicated. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 7, 9, 15-16, 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 7, 9, 15-16, 18, and 20 recite the limitation “respective ones”, this limitation renders the claim indefinite because it is unclear what structures of the semiconductor test structure is being defined as a respective one. For examination purposes, based on broadest reasonable interpretation, the examiner has interpreted this limitation as either respective sides, respective drain and source contacts/regions, or corresponding pairs. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim (s) 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsiao et al. (US20250046756A1) . Regarding Claim 1: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) comprising: a first side (FMLI-1 structure; Figs. 1 and 9; element FMLI-1); a second side (BMLI-1 structure; Figs. 1 and 9, element BLMI-1) located opposite the first side (Figs. 1 and 9, elements BLMI-1 and FMLI-1); a device layer (device layer; Figs. 1 and 9, element DL1) disposed between the first side and the second side (Figs. 1 and 9, elements FMLI-1, DL1, and BMLI-1), wherein the device layer comprises a plurality of devices (microelectronic devices; Fig. 3A elements T1 and T2); at least one first side wiring level (metal lines, metal layer; Fig. 9 elements 122 and M0-(X-2), paragraph 23) disposed on the first side (Fig. 9 elements 122, M0-(X-2), and FMLI-1); and at least one second side wiring level (metal lines, metal layer; Fig. 9 elements 122' and BM0-2, paragraphs 25-26) disposed on the second side (Fig. 9 elements 122', BM0-2, and BMLI-1); wherein two or more of the plurality of devices (Fig. 3A elements T1 and T2) are electrically connected to each other (Fig. 3A elements 110 and 112) through at least one contact structure (Fig. 3A elements 138, 136, 148, 149, and 144) connecting the at least one first side wiring level (fig. 3A elements 122 and M0) and the at least one second side wiring level (Fig. 3A elements 122' and BM0). Regarding Claim 2: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, wherein the at least one contact structure is disposed through the device layer between the first side and the second side (Region II; Fig. 3B/C elements 112, 144, 172, 136, and 138). Regarding Claim 3: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, wherein the at least one contact structure comprises at least one via (Figs. 1 and 3A-C, elements 160, 140, 144, 138, and 172) disposed through the device layer between the first side (Figs. 1 and 3A-C, element FMLI-1) and the second side (Figs. 1 and 3A-C, element BMLI-1). Regarding Claim 4: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, wherein the first side (FMLI-1) comprises a frontside (Fig. 1 element FS1) of the semiconductor test structure and the second side (BMLI-1) comprises a backside of the semiconductor test structure (Fig. 1 element BS1). Regarding Claim 5: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 4, wherein the at least one second side wiring level comprises a backside power rail (Fig. 1 and 9 elements BM0 and SPR, paragraphs 25 and 75). Regarding Claim 6: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, further comprising at least one dielectric layer (Figs. 3A-C element 142, paragraph 22), wherein the at least one first side wiring level (Figs. 3A-C element M0) is disposed in the at least one dielectric layer and comprises a plurality of contacts separated from each other by respective portions of the at least one dielectric layer (Figs. 3A-C elements 142 and 122). Regarding Claim 7: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 6, wherein respective ones of the plurality of contacts (Figs. 3A-C elements 122 and 122') are electrically connected to each other through a plurality of contact structures (Figs. 3A-C elements 138, 136, 148, 112, 144, and 149) connecting the at least one first side wiring level (Figs. 3A-C element M0) and the at least one second side wiring level (Figs. 3A-C element BM0), the plurality of contact structures including the at least one contact structure (Fig. 1 elements Region I/II). Regarding Claim 8: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, further comprising at least one dielectric layer (Figs. 3A-C element 146), wherein the at least one second side wiring level (Figs. 3A-C element BM0) is disposed in the at least one dielectric layer and comprises a plurality of contacts separated from each other by respective portions of the at least one dielectric layer (Figs. 3A-C elements 146 and 122'). Regarding Claim 9: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 8, wherein respective ones of the plurality of contacts (Figs. 3A-C elements 122 and 122') are electrically connected to each other through a plurality of contact structures (Figs. 3A-C elements 138, 136, 148, 112, 144, and 149) connecting the at least one first side wiring level (Figs. 3A-C element M0) and the at least one second side wiring level (Figs. 3A-B element BM0), the plurality of contact structures including the at least one contact structure (Fig. 1 elements Region I/II). Regarding Claim 10: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, wherein the plurality of devices comprise a plurality of transistors (Fig. 3A elements T1 and T2, paragraph 21), and wherein the at least one contact structure (Figs. 3A-B elements 138, 136, 148, 144, and 149) is disposed through a source/drain region (Fig. 3A element 112, paragraph 21) of a transistor of the plurality of transistors. Regarding Claim 11: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 1, wherein the plurality of devices comprise a plurality of transistors (Fig. 3A elements T1 and T2, paragraph 21) and the semiconductor test structure further comprises a source/drain contact (Figs. 3A-B element 136) connecting the at least one first side wiring level (M0) to a source/drain region (112) of a transistor of the plurality of transistors. Regarding Claim 12: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 11, wherein the at least one contact structure (Fig. 3B-C element Region II) is disposed through an additional source/drain region (112) adjacent the source/drain region of the transistor (Fig. 1 elements Region I and Region II). Regarding Claim 13: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) comprising: a plurality of first side wiring levels (metal lines, metal layer; Fig. 9 elements 122 and M0-(X-2), paragraph 23) disposed on a first side of the semiconductor test structure (FMLI-1 structure; Figs. 1 and 9; element FMLI-1); a plurality of second side wiring levels (metal lines, metal layer; Fig. 9 elements 122' and BM0-2, paragraphs 25-26) disposed on a second side (BMLI-1 structure; Figs. 1 and 9, element BLMI-1) of the semiconductor test structure, wherein the second side is located opposite the first side (Figs. 1 and 9, elements BLMI-1 and FMLI-1); and a device layer (device layer; Figs. 1 and 9, element DL1) disposed between the first side and the second side (Figs. 1 and 9, elements FMLI-1, DL1, and BMLI-1), wherein the device layer comprises a plurality of devices (microelectronic devices; Fig. 3A elements T1 and T2); wherein the plurality of first side wiring levels (M0-(X-2)) and the plurality of second side wiring levels (BM0-2) are serially connected through a plurality of contact structures (Fig. 1 elements Region I and Region II, paragraphs 26 and 33-34); and wherein a subset of the plurality of contact structures comprises a plurality of vias (Figs. 1 and 3A-C, elements 160, 138, 140, and 172) disposed through the device layer (DL1) between the first side (FMLI-1) and the second side (BMLI-1). Regarding Claim 14: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 13, wherein two or more of the plurality of devices (T1/T2) are electrically connected (Fig. 3A elements 112 and 110) to each other through one or more of the plurality of vias (Fig. 3A elements 140, 138, 136, 144, BV0 and V0). Regarding Claim 15: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 13, wherein the plurality of devices comprise a plurality of transistors (T1/T2), and wherein respective ones of the plurality of vias are disposed through respective epitaxial layers of respective transistors (Fig. 3A elements 136, 148, 112, 149, and 144, paragraph 21) of the plurality of transistors. Regarding Claim 16: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 13, wherein: portions of respective ones of the plurality of first side wiring levels are physically separated from each other by at least one dielectric layer on the first side (Figs. 3A-C and 9 elements 122, M0-(X-2), and 142 paragraph 22); and portions of respective ones of the plurality of second side wiring levels are physically separated from each other by at least one dielectric layer on the second side (Figs. 3A-C and 9 elements 122', BM0-Z, and 146 paragraph 22). Regarding Claim 17: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 13, wherein: the first side (FMLI-1) comprises a frontside of the semiconductor test structure (Fig. 1 element FS1) and the second side (BMLI-1) comprises a backside of the semiconductor test structure (Fig. 1 element BS1); and at least one of the plurality of second side wiring levels comprises a backside power rail (Fig. 1 and 9 elements BM0-Z and SPR, paragraphs 25 and 75). Regarding Claim 18: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) comprising: a first plurality of contact structures (Fig. 1 element Region I and FMLI-1) on a first side (Fig. 1 and 3A element FMLI-1) of a device layer (Figs. 1 and 3A, element DL1) comprising a plurality of devices (Fig. 3A elements T1 and T2), wherein respective ones of the first plurality of contact structures are connected to respective ones of the plurality of devices (Fig. 3A); and a second plurality of contact structures (Fig. 1 element Region I and BMLI-1) on a second side (Fig. 1 and 3A element BMLI-1) of the device layer (DL1); wherein the second side of the device layer is located opposite the first side (Figs. 1 and 9 elements BMLI-1, DL1, and FMLI-1); and wherein the first plurality of contact structures (FMLI-1) are serially connected to the second plurality of contact structures (BMLI-1) through a plurality of vias (Fig. 3A elements V0, BV0, 140, 138, 136, and 144) disposed through the device layer (DL1). Regarding Claim 19: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 18, wherein the first side (FMLI-1) of the device layer is on a frontside (Fig. 1 element FS1) of the semiconductor test structure and the second side (BMLI-1) of the device layer is on a backside of the semiconductor test structure (Fig. 1 element BS1). Regarding Claim 20: Hsiao discloses a semiconductor test structure (stacked chip structure/workpiece; Figs. 1 and 9, elements 100A and 200) according to claim 18, wherein the plurality of devices comprise a plurality of transistors (T1/T2), and wherein the respective ones of the first plurality of contact structures (Fig. 3A elements 136, 138, 140, and 144) are connected to respective source/drain regions (Fig. 3A element 112) of the respective ones of the plurality of devices. Citation of Pertinent Prior Art 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Greene et al. (WO 2025119506 A1), Zhou et al. (US 12615832 B2), Xie et al. (US 20240321747 A1), Xie et al. (US 20240105605 A1), Wang et al. (US 11777016 B2), Xie et al. (US 20230100113 A1) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chloë E Benton whose telephone number is (571)272-9976. The examiner can normally be reached Monday-Thursday: 8am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chloë E Benton/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899 Application/Control Number: 18/620,542 Page 2 Art Unit: 2899 Application/Control Number: 18/620,542 Page 3 Art Unit: 2899 Application/Control Number: 18/620,542 Page 4 Art Unit: 2899 Application/Control Number: 18/620,542 Page 5 Art Unit: 2899 Application/Control Number: 18/620,542 Page 6 Art Unit: 2899 Application/Control Number: 18/620,542 Page 7 Art Unit: 2899 Application/Control Number: 18/620,542 Page 8 Art Unit: 2899 Application/Control Number: 18/620,542 Page 9 Art Unit: 2899 Application/Control Number: 18/620,542 Page 10 Art Unit: 2899 Application/Control Number: 18/620,542 Page 11 Art Unit: 2899
