Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 07/22/2026 has been entered. Claims 1 – 16 are elected without traverse. Claims 17 – 20 are non-elected and canceled. Claims 1 – 16 remain pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pendharkar ( Pat. No. US 9865729 B1 ), hereinafter Pendharkar.
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Regarding Independent claim 1, Pendharkar teaches a semiconductor device, comprising:
a semiconductor layer ( Pendharkar, FIG. 3, 347; col. 4, line 6, epitaxial layer 347 );
a drain region ( Pendharkar, FIG. 1, 101, 223; FIG. 3, 223; col. 4, line 6, drain region 101 includes an n + region 223 that is diffused into nwell 220 ) disposed in the semiconductor layer (Pendharkar, FIG. 3, 347);
a source region ( Pendharkar, FIG. 1, 102, 225; FIG. 3, 225; col. 4, line 16, Source region 102 includes an n + region 225 that is diffused into pwell 222 ) disposed in the semiconductor layer;
a channel region ( Pendharkar, FIGs. 2 – 4, 230; col. 4, line 27, A channel region stripe 230 is located substantially parallel to and between the source region stripe 102 ( i.e. source region 225 ) and the drain region stripe 101 ( i.e. drain region 223 ) in dwell 222 ) disposed between the drain region ( Pendharkar, FIGs. 2 – 4, 101, 223 ) and the source region (Pendharkar, FIGs. 2 – 4, 102, 225);
a gate ( Pendharkar, FIGs. 3 – 5, 331; col. 4, line 54, A conductive gate layer 331 overlies comb shaped gate oxide 110 and comb shaped field oxide 212 ) disposed over the channel ( Pendharkar, FIGs. 2 – 4, 230; col. 4, line 34, A comb shaped gate oxide region stripe 110 overlays channel region stripe 230 ) region; and
first ( Pendharkar, FIGs. 2 – 5, 110; col. 4, line 54, comb shaped gate oxide 110 ) and second ( Pendharkar, FIGs. 2 – 5, 212; col. 4, line 54, comb shaped field oxide 212 ) insulating layers disposed between the gate ( Pendharkar, FIGs. 3 – 5, 331 ) and the semiconductor layer ( Pendharkar, FIG. 3, 347 ), wherein sections of the first ( Pendharkar, FIGs. 2 – 5, 110 ) insulating layer and sections of the second ( Pendharkar, FIGs. 2 – 5, 212 ) insulating layer alternate ( Pendharkar, FIG. 2, 110, 212 ) along a first direction perpendicular to a second direction defined between the drain region ( Pendharkar, FIG. 1, 101, 223; FIG. 3, 223 ) and the source region ( Pendharkar, FIG. 1, 102, 225; FIG. 3, 225 ), each of the sections of the first ( Pendharkar, FIGs. 2 – 5, 110 ) insulating layer having a first thickness and each of the sections of the second ( Pendharkar, FIGs. 2 – 5, 212 ) insulating layer having a second thickness greater ( Pendharkar, FIGs. 2 – 5, 212 thicker than 110 ) than the first thickness ( Pendharkar, col. 4, line 49, Between each thin gate segment there is a finger of thick field oxide region 212 ).
Regarding claim 2, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
wherein the second ( Pendharkar, FIGs. 2 – 5, 212; col. 4, line 54, comb shaped field oxide 212; col. 3, line 1, Field oxide is typically formed as a thick region of silicon dioxide ) insulating layer comprises an oxide material.
Regarding claim 3, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
wherein the second ( Pendharkar, FIGs. 2 – 5, 212 ) insulating layer comprises a nitride material ( Pendharkar, col. 6, line 60, While a comb shaped field oxide feature with field oxide fingers that lie between each of the fingers of the comb shaped gate oxide was described herein, in another embodiment a different type of comb shaped dielectric may be used. For example, a low k dielectric … may be used. A high k dielectric … may be used ).
Regarding claim 4, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
wherein each of the sections of the second ( Pendharkar, FIGs. 2 – 5, 212 ) insulating layer comprises tapered sidewalls ( Pendharkar, FIGs. 2 – 5, 212 is taper toward the adjacent thin gate oxide sections 110 ).
Regarding claim 5, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
trench insulating sections ( Pendharkar, abstract, The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance; col. 3, line 1, Field oxide is typically formed as a thick region of silicon dioxide; col. 4, line 49, Between each thin gate segment there is a finger of thick field oxide region 212 ) disposed in the semiconductor layer and in alignment, in the first direction, with the sections of the first ( Pendharkar, FIGs. 2 – 5, 110 ) insulating layer.
Regarding claim 6, Pendharkar teaches the semiconductor device as claimed in claim 5, on which this claim is dependent, Pendharkar further teaches:
wherein the trench insulating sections comprise shallow trench isolation regions ( Pendharkar, col. 3, line 1, Field oxide is typically formed as a thick region of silicon dioxide, however, other known or later developed dielectrics may be used to form the comb shaped structure 110. In this example, a similar comb shaped gate oxide region stripe 111 overlays the channel region stripe between source region 102 and drain region 103 ).
Regarding claim 7, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
wherein the gate ( Pendharkar, FIGs. 3, 5, 331 ) comprises recessed ( Pendharkar, FIGs. 3, 5, 331 above 110-1 and 110-2 ) portions in alignment with the sections of the first ( Pendharkar, FIGs. 2 – 5, 110 ) insulating layer.
Regarding claim 8, Pendharkar teaches the semiconductor device as claimed in claim 7, on which this claim is dependent, Pendharkar further teaches:
wherein the recessed ( Pendharkar, FIGs. 3, 5, 331 above 110-1 and 110-2 ) portions extend in the second direction ( Pendharkar, FIGs. 3, 5, along 212 to 110 ).
Regarding claim 9, Pendharkar teaches the semiconductor device as claimed in claim 1, on which this claim is dependent, Pendharkar further teaches:
wherein the semiconductor device comprises a laterally-diffused metal-oxide semiconductor (LDMOS) transistor ( Pendharkar, FIGs. 1 – 5, 100; col. 3, line 60, LDMOS transistor 100 ).
Regarding Independent claim 10, Pendharkar teaches a semiconductor device, comprising:
a semiconductor layer ( Pendharkar, FIG. 3, 347; col. 4, line 6, epitaxial layer 347 );
a drain region ( Pendharkar, FIG. 1, 101, 223; FIG. 3, 223; col. 4, line 6, drain region 101 includes an n + region 223 that is diffused into nwell 220 ) disposed in the semiconductor layer (Pendharkar, FIG. 3, 347);
a source region ( Pendharkar, FIG. 1, 102, 225; FIG. 3, 225; col. 4, line 16, Source region 102 includes an n + region 225 that is diffused into pwell 222 ) disposed in the semiconductor layer (Pendharkar, FIG. 3, 347);
a channel region ( Pendharkar, FIGs. 2 – 4, 230; col. 4, line 27, A channel region stripe 230 is located substantially parallel to and between the source region stripe 102 ( i.e. source region 225 ) and the drain region stripe 101 ( i.e. drain region 223 ) in dwell 222 ) disposed between the drain region ( Pendharkar, FIGs. 2 – 4, 101, 223 ) and the source region ( Pendharkar, FIGs. 2 – 4, 102, 225 );
a gate ( Pendharkar, FIGs. 3 – 5, 331; col. 4, line 54, A conductive gate layer 331 overlies comb shaped gate oxide 110 and comb shaped field oxide 212 ) disposed over the channel ( Pendharkar, FIGs. 2 – 4, 230; col. 4, line 34, A comb shaped gate oxide region stripe 110 overlays channel region stripe 230 ) region; and
gate dielectric ( Pendharkar, FIGs. 2 – 5, 110; col. 4, line 54, comb shaped gate oxide 110 ) and field dielectric ( Pendharkar, FIGs. 2 – 5, 212; col. 4, line 54, comb shaped field oxide 212 ) layers disposed between the gate ( Pendharkar, FIGs. 3 – 5, 331 ) and the semiconductor layer ( Pendharkar, FIG. 3, 347 ), wherein sections of the gate dielectric ( Pendharkar, FIGs. 2 – 5, 110 ) layer and sections of the field dielectric ( Pendharkar, FIGs. 2 – 5, 212 ) layer alternate ( Pendharkar, FIG. 2, 110, 212 ) along a first direction perpendicular to a second direction defined between the drain region ( Pendharkar, FIG. 1, 101, 223; FIG. 3, 223 ) and the source region ( Pendharkar, FIG. 1, 102, 225; FIG. 3, 225 ), each of the sections of the gate dielectric ( Pendharkar, FIGs. 2 – 5, 110 ) layer having a first thickness and each of the sections of the field dielectric ( Pendharkar, FIGs. 2 – 5, 212 ) layer having a second thickness greater ( Pendharkar, FIGs. 2 – 5, 212 thicker than 110 ) than the first thickness ( Pendharkar, col. 4, line 49, Between each thin gate segment there is a finger of thick field oxide region 212 ).
Regarding claim 11, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
wherein the field dielectric ( Pendharkar, FIGs. 2 – 5, 212; col. 4, line 54, comb shaped field oxide 212; col. 3, line 1, Field oxide is typically formed as a thick region of silicon dioxide ) layer comprises an oxide material.
Regarding claim 12, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
wherein the field dielectric ( Pendharkar, FIGs. 2 – 5, 212 ) layer comprises a nitride material ( Pendharkar, col. 6, line 60, While a comb shaped field oxide feature with field oxide fingers that lie between each of the fingers of the comb shaped gate oxide was described herein, in another embodiment a different type of comb shaped dielectric may be used. For example, a low k dielectric … may be used. A high k dielectric … may be used ).
Regarding claim 13, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
wherein each of the sections of the field dielectric ( Pendharkar, FIGs. 2 – 5, 212 ) layer comprises tapered sidewalls ( Pendharkar, FIGs. 2 – 5, 212 is taper toward the adjacent thin gate oxide sections 110 ).
Regarding claim 14, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
trench insulating sections ( Pendharkar, abstract, The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance; col. 3, line 1, Field oxide is typically formed as a thick region of silicon dioxide; col. 4, line 49, Between each thin gate segment there is a finger of thick field oxide region 212 ) disposed in the semiconductor layer and in alignment, in the first direction, with the sections of the gate dielectric ( Pendharkar, FIGs. 2 – 5, 110 ) layer.
Regarding claim 15, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
wherein the gate ( Pendharkar, FIGs. 3, 5, 331 ) comprises recessed ( Pendharkar, FIGs. 3, 5, 331 above 110-1 and 110-2 ) portions in alignment with the sections of the gate dielectric ( Pendharkar, FIGs. 2 – 5, 110 ) layer and extending in the second direction ( Pendharkar, FIGs. 3, 5, along 212 to 110 ).
Regarding claim 16, Pendharkar teaches the semiconductor device as claimed in claim 10, on which this claim is dependent, Pendharkar further teaches:
wherein the semiconductor device comprises a laterally-diffused metal-oxide semiconductor (LDMOS) transistor ( Pendharkar, FIGs. 1 – 5, 100; col. 3, line 60, LDMOS transistor 100 ).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Da-Wei Lee whose telephone number is 703-756-1792. The examiner can normally be reached M -̶ F 8:00 am -̶ 6:00 pm.
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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