Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket number: P202302216US01/IBMP1498US
Filling Date: 03/28/24
Inventor: Schupp et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Claims 1-18 in the reply filed on08/05/26 is acknowledged. The traversal is on the ground(s) that rejoinder the method claims 19-20 once the claims 1 and 16 are found allowable.
If the method independent claim 19 includes the allowable subject matter same as the claim 1 or 16, then claims 19-20 will be rejoined.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Veldhorst et al (US 2024/0289673 A1, Veld hereinafter).
Regarding claim 1, Veld discloses a semiconductor structure (Figs. 1-4, abstract) comprising: a semiconductor substrate 102, 104 (Paras. 56-57); a gate electrode 106, 108 (Para. 58) separated from the semiconductor substrate 102, 104 by a strain isolation gap 210 (abstract, claim does not define the strain isolation gap); and a quantum dot region 110 (Para. 58) formed in the substrate 102, 104 underneath the gate electrode 106, 108, wherein the quantum dot region 110 is configured to form a quantum dot upon energization (Para. 60) of the gate electrode 106, 108, and wherein the quantum dot 110 is configured to host a spin (Para. 75).
Veld does not explicitly disclose strain isolation gap. However, Veld discloses a layer 210 (abstract) same as instant application which is between gate electrode 106, 108 and the substrate 102, 104. Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to use the layer 210 as a strain isolation layer for isolating the strain (Fig. 2, abstract).
Regarding claim 2, Veld discloses the semiconductor structure of claim 1, wherein the gate electrode is a first gate electrode 106, further comprising a second gate electrode 108 adjacent to the first gate electrode 106, wherein the first gate electrode 106 is a plunger gate electrode (Para. 58), wherein the second gate electrode 108 is a barrier gate electrode (Para. 58) that is also separated from the semiconductor substrate 102, 104 by a strain isolation gap 210.
Regarding claim 16, Veld discloses a quantum processing unit (Figures 1-4) comprising: an array of quantum semiconductor structures 110, wherein each quantum semiconductor structure 110 comprises: a semiconductor substrate 102, 104; a gate electrode 106, 108 separated from the semiconductor substrate 102, 104 by a strain isolation gap 210; and a quantum dot region 110 formed in the substrate 102 underneath the gate electrode 106. 108, wherein the quantum dot region 110 is configured to form a quantum dot upon energization of the gate electrode 106, 108, and wherein the quantum dot 110 is configured to host a spin; a voltage source Vb, Vg (abstract) coupled to the gate electrode 106, 108 of each quantum semiconductor structure 110; and a controller Vb, Vg (abstract) coupled to the voltage source, wherein the controller is configured to cause the voltage source to selectively energize the gate electrode of each quantum semiconductor structure (Abstract).
Veld does not explicitly disclose strain isolation gap. However, Veld discloses a layer 210 (abstract) same as instant application which is between gate electrode 106, 108 and substrate 102, 104. Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to use the layer 210 as a strain isolation layer for isolating the strain (Fig. 2, abstract).
Regarding claim 17, Veld discloses the quantum processing unit of claim 16, wherein, for one or more of the semiconductor structures 110, the gate electrode is a first gate electrode 106, the one or more of the semiconductor structures further comprising a second gate electrode 108 adjacent to the first gate electrode 106, wherein the first gate electrode 106 is a plunger gate electrode, wherein the second gate electrode 108 is a barrier gate electrode, and wherein the second gate electrode 108 also is separated from the semiconductor substrate 102, 104 by a strain isolation gap 210.
Allowable Subject Matter
Claims 3-15 and 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817
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