Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed November 17th, 2025, with respect to the rejections of the independent claims have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Fleischman et al (US 2013/0007418).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mellempudi et al (US 2024/0045691, herein Mellempudi) in view of Fleischman et al (US 2013/0007418, herein Fleischman.
Regarding claim 1, Mellempudi teaches an integrated circuit comprising:
a first computing region and a second computing region, wherein the integrated circuit performs computations according to an out-of-order execution scheduling scheme (Figs 12-14, [0112-0113], out of order execution);
a first retirement register that stores a first set of entries comprising information pertaining to results of computations performed by the first computing region (Figs 12-14, [0112], first retirement register file of first core); and
a second retirement register that stores a second set of entries comprising information pertaining exclusively to results of computations performed by the second computing region (Figs 12-14, [0112], [0120], second retirement register file of another core).
Mellempudi fails to teach wherein the first retirement register stores information pertaining to results of computations performed by the first and second computing regions.
Fleischman teaches a integrated circuit wherein a first retirement register stores a first of entries comprising information pertaining to results of computations performed by a first and second computing region ([0019-0022], [0024-0025], retire unit & queue comprising entries for completed instructions, [0024], merged retire queue including results from separate operation types i.e. floating-point or integer, Fig 1, floating point and integer units as distinct computing regions).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Mellempudi and Fleischman to utilize a merged retirement register. While Mellempudi does not explicitly state that the exemplary retirement register files may include both dedicated/exclusive sections and a merged section including results for both computing regions, both Mellempudi and Fleischman describe techniques for handling the retirement of instructions which have been computed in separate regions (Mellempudi Fig 13, different regions of execution circuitry & Fleischman Fig 1, separate FP and integer units). Therefore, allowing the retirement circuit of Mellempudi to track results from multiple types of execution regions at once, as disclosed by Fleischman, would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein: the second computing region comprises a floating point unit; and wherein the second set of entries comprises information pertaining to results of computations performed by the floating point unit (Mellempudi [0112], [0114], various floating point operations).
Regarding claim 3, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein the second retirement register stores each entry in the second set of entries in association with a retirement identifier that maps the entry to a position in a global retirement queue, the global retirement queue implemented with the first retirement register specifying a retirement order for results of computations performed by both the first and second computing regions (Mellempudi [0112], [0228], retirement circuit and retirement queue, Fleischman Fig 3, [0024-0025], merged retirement queue tracking instructions via pointers).
Regarding claim 4, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein the first set of entries comprises information necessary to properly retire calculations performed by the first computing region and the second computing region (Mellempudi [0120], [0228], reorder buffer, retirement register files, and retirement queues to implement accurate retirement order).
Regarding claim 5, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 4, wherein the first set of entries stored in the first retirement register comprises pointers to information stored in the second retirement register (Mellempudi [0112], instruction pointers stored in register files).
Regarding claim 6, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein the second set of entries pertain to results of a single data type (Mellempudi [0112], typed register files).
Regarding claim 7, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 6, wherein the single type is the result of floating point operations (Mellempudi [0112], various floating point register types).
Regarding claim 8, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein the second retirement register is physically disposed within the second computing region (Mellempudi Figs 12-14, [0112], register files and retirement circuit in each core).
Regarding claim 9, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, further comprising a retirement logic management component that ensures results of computations performed by the first computing region and the second computing region are processed according to the out-of-order execution scheduling scheme (Mellempudi [0228], reorder buffer for performing OoO execution).
Regarding claim 10, The combination of Mellempudi and Fleischman teaches the integrated circuit of claim 1, wherein the integrated circuit comprises a central processing unit (CPU) (Mellempudi [0047], [0217], cores including CPUs).
Claims 11-19 refer to a system embodiment of the integrated circuit embodiment of claims 1-9. The above rejections for claims 1-9 are thus applicable to claims 11-19, respectively.
Claim 20 refers to a method embodiment of the integrated circuit embodiment of claim 1. The above rejection for claim 1 is thus applicable to claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Anderson (US 2019/0243646) discloses a processor that uses dedicated writeback queues.
Luo (US 2003/0093702) discloses a processor with a dedicated writeback register.
Edmondson (US 5,471,591) discloses a processor with a retire queue for merging results from different pipelines.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183