Prosecution Insights
Last updated: July 17, 2026
Application No. 18/620,984

SEMICONDUCTOR STRUCTURE

Non-Final OA §103
Filed
Mar 28, 2024
Priority
Mar 06, 2024 — TW 113108237
Examiner
SLUTSKER, JULIA
Art Unit
Tech Center
Assignee
Powerchip Semiconductor Manufacturing Corporation
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
828 granted / 1077 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+12.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
44 currently pending
Career history
1126
Total Applications
across all art units

Statute-Specific Performance

§103
87.3%
+47.3% vs TC avg
§102
6.9%
-33.1% vs TC avg
§112
3.9%
-36.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1077 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-4, and 6-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ling (US 2024/0071936) in view of Chung (US 2020/0212033). Regarding claim 1, Ling discloses a semiconductor structure, comprising: an interposer (Fig. 1, numeral 12) ([0013]) comprising: a substrate (120) ([0015]); a redistribution layer (RDL) (126) ([0015]) located on the substrate (120); a first integrated passive device (IPD) (124) located in the substrate (120) ([0015]). Ling does not disclose a second IPD located in the RDL. Chung however discloses a second IPD located in the RDL ([0006]; [0026]) (Figs. 10, 11). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Ling with Chung to have a second IPD located in the RDL for the purpose of providing ESD protection (Chung, [0026]). Regarding claim 2, Ling in view of Chung discloses wherein the first IPD (Ling, Fig.1, numeral 124) and the second IPD (Ling, Fig, 1, numeral 126; Chung, Fig.10, numeral C11, C14) are electrically connected to each other (Ling, [0015]; note (125) and (124) are electrically connected). Regarding claim 3, Ling does not disclose wherein the first IPD and the second IPD are connected in series. Chung however discloses that IPD devices are connected in series (Fig.10; numerals C11, C14). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to connected the first IPD and the second IPD in series for the purpose effectively forming a protective apparatus (Chung, [0054]). Regarding claim 4, Ling does not disclose wherein the first IPD and the second IPD are connected in parallel. Chung however discloses that IPD devices are connected in parallel (Fig.10; numerals C11, C12). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to connected the first IPD and the second IPD in parallel for the purpose effectively forming a protective apparatus (Chung, [0054]). Regarding claim 6, Ling in view of Chung discloses wherein the first IPD (Ling, numeral 124) and the second IPD (Fig.10, numeral 311) are separated from each other (Fig. 10; note: lower layers in (101)). Regarding claim 7, Ling does not disclose wherein the second IPD overlaps the first IPD. Chung however discloses overlapping IPDs (Fig. 11). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to overlap the second IPD and the first IPD for the purpose of reducing layout area of capacitors (Chung, [0059]). Regarding claim 8, Ling in view of Chung does not disclose wherein the second IPD does not overlap the first IPD. Chung however discloses that positions of the second IPD can be adjusted to optimize a layout structure based on design requirements ([0067]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have the second IPD not overlapping the first IPD for the purpose of optimization a layout structure. Regarding claim 9, Ling discloses wherein the first IPD (124) comprises a capacitor ([0022]). Regarding claim 10, Chung discloses wherein the second IPD comprises a capacitor (Fig.10). Regarding claim 11, Chung discloses wherein the RDL comprises: a dielectric layer (Fig.2, lower layer in (101)) located on the substrate (200); an interconnect structure (PP1) located in the dielectric layer; and a pad located above the interconnect structure and located in the dielectric layer ([0036])). Regarding claim 12, Ling discloses wherein the first IPD (124) is electrically connected to the interconnect structure (in (125). Regarding claim 13, Chung discloses wherein the second IPD (Fig.10, numeral C13) is electrically connected to the interconnect structure (PR2). Regarding claim 14, Chung discloses wherein the second IPD (Fig.10, numeral C13) is located in the dielectric layer (Fig.10). Regarding claim 15, Chung discloses wherein the dielectric layer (M1; [0042]) comprises a first surface and a second surface opposite to each other, and the first surface is adjacent to the substrate (Fig.2, numeral 200). Regarding claim 16, Ling in view of Chung discloses wherein the first IPD (Lin, numeral 124) and the second IPD (Chung, Fig.2, numeral 130) are adjacent to the first surface, and the pad is adjacent to the second surface ([0036]). Regarding claim 17, Chung discloses a die (Fig.2, numeral 120) located on the second surface and electrically connected to the pad ([0036]). Regarding claim 18, Chung discloses a connection terminal (123) located between the die (120) and the pad (SP1) ([0029]). Regarding claim 19, Ling discloses wherein the interposer (Fig.1, numeral 12) further comprises: a through-substrate via (TSV) (123) passing through the substrate (120). Regarding claim 20, Chung discloses wherein the TSV extends into the dielectric layer (Fig.2). Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The search of the prior art does not disclose or reasonably suggest wherein the first IPD and the second IPD are electrically insulated from each other as required by claim 5. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/Primary Examiner, Art Unit 2891
Read full office action

Prosecution Timeline

Mar 28, 2024
Application Filed
Jun 10, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12677604
GROUP III NITRIDE SUBSTRATE WITH OXYGEN GRADIENT, METHOD OF MAKING, AND METHOD OF USE
3y 7m to grant Granted Jul 07, 2026
Patent 12677644
ISOLATION STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
2y 11m to grant Granted Jul 07, 2026
Patent 12677465
SOURCE/DRAIN EXTENSION WITH SPACER LAYERS
2y 6m to grant Granted Jul 07, 2026
Patent 12672397
LIGHT-EMITTING DEVICES, PREPARATION METHOD THEREOF, AND DISPLAY PANELS
2y 6m to grant Granted Jun 30, 2026
Patent 12660531
METHOD OF MANUFACTURING Si-SiC-BASED COMPOSITE STRUCTURE
3y 4m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+12.3%)
2y 5m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1077 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month