DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the device in the reply filed on 6/10/2026 is acknowledged.
Information Disclosure Statement
Applicant has provided multiple Foreign reference used in Foreign office actions. The office action cites the body of the reference and not just an abstract. To be full considered a translation of the documents should be provided.
The requirement for a concise explanation of relevance is limited to information that is not in the English language. The explanation required is limited to the relevance as understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information at the time the information is submitted to the Office. If a complete translation of the information into English is submitted with the non-English language information, no concise explanation is required. There is no requirement for the translation to be verified, including reliable machine translations. An English-language equivalent application may be submitted to fulfill this requirement if it is, in fact, a translation of a foreign language application being listed in an information disclosure statement. The English language equivalent application should be separately listed and identified as an English language equivalent in the information disclosure statement. Submission of an English language abstract of a reference, such as one generated by a foreign patent office, may fulfill the requirement for a concise explanation. Where the information listed is not in the English language, but was cited in a search report or other action by a foreign patent office in a counterpart foreign application, the requirement for a concise explanation of relevance can be satisfied by submitting an English-language version of the search report or action which indicates the degree of relevance found by the foreign office. This may be an explanation of which portion of the reference is particularly relevant, to which claims it applies, or merely an “X”, “Y”, or “A” indication on a search report. The requirement for a concise explanation of non-English language information would not be satisfied by a statement that a reference was cited in the prosecution of a United States application which is not relied on under 35 U.S.C. 120.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “11” has been used to designate both chip stages and connectors. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: It is unclear which portion is to be identified as the connector both element 11 and 23 are designated as a connector.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang 2155788542 cited by applicant only abstract provided in view of Wang 102082100 cited by applicant only abstract provided.
Huang teaches A semiconductor device assembly, comprising: metal frames (figures item 1) and semiconductor device units (item 2); wherein the metal frames comprise chip stages (large flat region of item 1);
Huang states: The step of elastically connecting the lead frame with the pin clamping piece is as follows:
a. step one, providing a lead frame ;
b. step two, coating tin paste on the base island area of the lead frame (this region is the chip stage);
c. step three, in the step two island coating tin paste area planting chip;
the back surface of the chip is provided with a drain electrode, the front surface is provided with a source electrode and a gate electrode, the drain electrode is combined with the solder paste;
d. step four, coating solder paste on the source electrode and the grid electrode on the front surface of the chip by the clamping welding device;
e. step five, mounting the pin clamping piece on the appointed area of the chip through the suction nozzle of the clamping welding device, at the same time, clamping the pin clamping piece into the elastic clamping groove through the clamping welding device suction nozzle lower pressing pin clamping piece;
f. step six, carrying out reflow soldering to the lead frame for clamping and welding;
step seven, the lead frame after reflow soldering using plastic package material for plastic package;
g. step eight, the plastic package of the lead frame for punching operation, the original array plastic package body is separated into a single product.
; the semiconductor device units comprise chips (item2), pins (figure 3 item 5 elongated portion upward and downward item 6), and connectors (large plate region at the top and bottom); the chips and the pins are arranged above the metal frames (steps c-e the clamp is clamped over the chip thus the lead frame is below); each of the connectors is configured to electrically connect an electrode of a corresponding chip with a corresponding pin (step d-f the clamp electrically connected to the source drain and grid electrode); the semiconductor device units are paired to form at least one semiconductor device pair (figures 1-3 items 2 are paired by the shape of the clap figure 3 item 5); each of the chips is arranged on a corresponding chip stage (figure 1); the pins of each semiconductor device pair are connected (figure 1 and 2); the connectors of each semiconductor device pair are away from each other (figure 1 and 2 the relative locations of the connection regions); the semiconductor device units are arranged in sequence along a length direction of the metal frames or a width direction of the metal frames (figure 1)
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Huang does not teach encapsulation layers are arranged along an arrangement direction of the semiconductor device units; the encapsulation layers are arranged above the chip stages.
Wang teaches encapsulation layers are arranged along an arrangement direction of the semiconductor device units; the encapsulation layers are arranged above the chip stages (figures 2a-2c item 14) along the arrangement direction.
Thus, it would have been obvious to one ordinary skill in the art at the time of filing to form encapsulation layers are arranged along an arrangement direction of the semiconductor device units; the encapsulation layers are arranged above the chip stages to use conventional encapsulation techniques to provide expected outcome of encapsulated dies that would allow mass encapsulation while allow the device to singulated to ensure encapsulation while reducing the amount of encapsulation used.
b. As to claim 2, Huang teaches a clip (FIG. 3 is a schematic view showing the structure of the pin clip in FIG. 1.)
Huang does not state copper however it was known to form clips from copper to provide good thermal and electrically conductivity.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the clip from copper for good thermal and electrically conductivity.
c. As to claim 3, Applicant does not state the connectors are wire and the wires are wherein the bonding wires are selected from gold wires, copper wires, aluminum wires, aluminum strips, or a combination thereof. Thus, the copper clips still read on the claims. It noted the elongated portions from clip 5 can be thought of copper wires.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Stoek 11545459 is similar provides clip (item 212 over the chips 102 on the lead frame 200 connected the clip connect the terminals item 202 and 204).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William F. Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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