DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “144B” in Figure 1C has been used to designate both “Top Source/Drain Region” and “2nd Bottom Source/Drain Region” (Also, 1st Bottom Source/Drain Region should be 144B, instead). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2022/0084561).
Regarding claim 1, Chen et al. discloses, as shown in Figures 1-2, a semiconductor device comprising:
a memory array (SRAM, [0008]) comprising:
a first ground rail on a backside of the memory array (part of the backside power delivery network, [0026]); and
a first voltage drain to drain (VDD) rail on a frontside of the memory array (part of the frontside power delivery network, [0025]); and
a logic array (periphery, [0008]) comprising:
a second ground rail on a backside of the logic array (part of the backside power delivery network, [0026]); and
a second VDD rail on the backside of the logic array (part of the backside power delivery network, [0026]).
Regarding claim 9, Chen et al. discloses, as shown in Figures 1-2, a method for fabricating a semiconductor device comprising:
forming a memory array (SRAM, [0008]), comprising:
forming a first ground rail on a backside of the memory array (part of the backside power delivery network, [0026]); and
forming a first voltage drain to drain (VDD) rail on a frontside of the memory array (part of the frontside power delivery network, [0025]); and
forming a logic array (periphery, [0008]), comprising:
forming a second ground rail on a backside of the logic array (part of the backside power delivery network, [0026]); and
forming a second VDD rail on a frontside of the logic array (part of the frontside power delivery network, [0026]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 -8 and 10-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2022/0084561) in view of Liebmann et al. (US 2020/0135718).
Regarding claims 2 and 10, Chen et al. discloses the claimed invention including the semiconductor device as explained in the above rejection. Chen et al. does not disclose the memory array further comprises a first top transistor stacked over a first bottom transistor;
the first top transistor comprises:
a first top source/drain region; and
a first contact connecting the first top source/drain region to the first VDD rail through a first top via; and
the first bottom transistor comprises:
a first bottom source/drain region; and
a second bottom source/drain region.
However, Liebman et al. discloses a memory array comprises a first top transistor stacked over a first bottom transistor;
the first top transistor comprises:
a first top source/drain region; and
a first contact (SDC) connecting the first top source/drain region to the first VDD rail (PC) through a first top via (V); and
the first bottom transistor comprises:
a first bottom source/drain region; and
a second bottom source/drain region.
Note Figures 5-8 of Liebmann et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the memory array of Chen et al. having the structure (complementary field effect transistors) as claimed, such as taught by Liebmann et al. in order to have the desired structure to perform the desired function.
Regarding claim 3, Chen et al. and Liebmann et al. disclose the memory array further comprises:
a first backside contact (SDC) connecting the first bottom source/drain region to the first ground rail; and
a second contact (SDC) connecting the second bottom source/drain region to a bitline through a second top via.
Regarding claim 4, Chen et al. and Liebmann et al. disclose at least one of the first top transistor or the first bottom transistor is a field-effect transistor (FET).
Regarding claim 5, Chen et al. and Liebmann et al. disclose the memory array is a Static Random Access Memory (SRAM) device ([0009] or [0017]).
Regarding claims 6 and 12, Chen et al. discloses the claimed invention including the semiconductor device as explained in the above rejection. Chen et al. does not disclose the logic array further comprises a second top transistor stacked over a second bottom transistor;
the second top transistor comprises:
a second top source/drain region;
a second top contact connecting the second top source/drain region to the second VDD rail through a deep via; and
the second bottom transistor comprises a third bottom source/drain region.
However, Liebman et al. discloses a logic array comprises a second top transistor stacked over a second bottom transistor;
the second top transistor comprises:
a second top source/drain region;
a second top contact (SDC) connecting the second top source/drain region to the second VDD rail through a deep via (V); and
the second bottom transistor comprises a third bottom source/drain region.
Note Figures 5-8 of Liebmann et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the logic array of Chen et al. having the structure (complementary field effect transistors) as claimed, such as taught by Liebmann et al. in order to have the desired structure to perform the desired function.
Regarding claim 7, Chen et al. and Liebmann et al. disclose the second bottom transistor further comprises a second backside contact () connecting the third bottom source/drain region to the second ground rail
Regarding claim 8, Chen et al. and Liebmann et al. disclose least one of the second top transistor or the second bottom transistor is a field-effect transistor (FET).
Regarding claim 14, Chen et al. discloses, as shown in Figures 1-2, a semiconductor device comprising:
a memory array (SRAM, [0008]) comprising a first top source/drain region, and a first contact connecting the first top source/drain region to a memory voltage drain to drain (VDD) rail, wherein the memory VDD rail is located on a frontside of the memory array (part of the frontside power delivery network, [0025]); and
a logic array (periphery, [0008]) comprising a logic ground rail and a logic VDD rail, wherein the logic ground rail and the logic VDD rail are located on a backside of the logic array (part of the backside power delivery network, [0026]).
Chen et al. does not disclose the first contact connecting the first top source/drain region to the memory voltage drain to drain (VDD) rail through a first top via. However, Liebmann et al. discloses a source/drain region connects to the voltage rail through a via (V). Note Figures 5-8 of Liebmann et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to connect the first top source/drain region of Chen et al. to a memory voltage drain to drain (VDD) rail through a first top via, such as taught by Liebmann et al. in order to connect the multi-interconnect levels together to perform the desired function.
Regarding claim 15, Chen et al. and Liebmann et al. disclose the memory array further comprises a memory ground rail on a backside of the memory array.
Regarding claim 16, Chen et al. and Liebmann et al. disclose the memory array further comprises a first top transistor stacked over a first bottom transistor; and the first bottom transistor comprises: a first bottom source/drain region; and a second bottom source/drain region.
Regarding claim 17, Chen et al. and Liebmann et al. disclose the memory array further comprises: a first backside contact connecting a first bottom source/drain region to a memory ground rail; and a second contact connecting a second bottom source/drain region to a bitline through a second top via.
Regarding claim 18, Chen et al. and Liebmann et al. disclose at least one of the first top transistor and the first bottom transistor is a field-effect transistor (FET).
Regarding claim 19, Chen et al. and Liebmann et al. disclose the memory array is a Static Random Access Memory (SRAM) device [0008].
Regarding claim 20, Chen et al. and Liebmann et al. disclose the logic array further comprises a second top transistor stacked over a second bottom transistor; the second top transistor comprises: a second top source/drain region; and a second top contact connecting the second top source/drain region to the logic VDD rail through a deep top via; and the second bottom transistor comprises a third bottom source/drain region [Figures 5-8].
Regarding claim 21, Chen et al. and Liebmann et al. disclose the second bottom transistor further comprises a second backside contact connecting the third bottom source/drain region to the logic ground rail [Figures 5-8].
Regarding claim 22, Chen et al. discloses, as shown in Figures 1-2, a method of fabricating a semiconductor:
forming a memory array (SRAM, [0008]) comprising:
forming a first top source/drain region; and
forming a first contact connecting the first top source/drain region to a memory voltage drain to drain (VDD) rail, wherein the memory VDD rail is located on a frontside of the memory array (part of the frontside power delivery network, [0025]); and
forming a logic array (periphery, [0008]) comprising:
forming a logic ground rail; and
forming a logic VDD rail, wherein the logic ground rail and the logic VDD rail are located on a backside of the logic array (part of the backside power delivery network, [0026]).
Chen et al. does not disclose forming the first contact connecting the first top source/drain region to the memory voltage drain to drain (VDD) rail through a first top via. However, Liebmann et al. discloses a source/drain region connects to the voltage rail through a via (V). Note Figures 5-8 of Liebmann et al. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to connect the first top source/drain region of Chen et al. to a memory voltage drain to drain (VDD) rail through a first top via, such as taught by Liebmann et al. in order to connect the multi-interconnect levels together to perform the desired function.
Regarding claim 23, Chen et al. and Liebmann et al. disclose the method further comprising: forming a first top transistor; and forming a top bottom transistor; and stacking the first top transistor over a first bottom transistor, wherein forming the first bottom transistor comprises: forming a first bottom source/drain region; and forming a second bottom source/drain region [Figures 5-8].
Regarding claim 24, Chen et al. and Liebmann et al. disclose forming the memory array further comprises: forming a first backside contact connecting a first bottom source/drain region to a memory ground rail; and forming a second contact connecting a second bottom source/drain region to a bitline through a second top via [Figures 5-8].
Regarding claim 25, Chen et al. and Liebmann et al. disclose forming the logic array further comprises: forming a second top transistor; and forming a second bottom transistor and stacking the second top transistor over the second bottom transistor, wherein: forming the second top transistor comprises: forming a second top source/drain region; and forming a second top contact connecting the second top source/drain region to the logic VDD rail through a deep via (V); and forming the second bottom transistor comprises forming a third bottom source/drain region [Figures 5-8].
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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