DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (Claim 1-9) in the reply filed on 08/04/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US PGpub: 2023/0100600 A1), hereinafter Tran, in view of Tran.
Regarding claim 1, Tran teaches a semiconductor device, comprising:
a plurality of first structures (having WL1….M, FIG. 7C), extending in a first direction (as in FIG. 7C) and spaced apart from each other in a second direction intersecting the first direction (as in FIG. 7C), each of the first structures comprising a word line (having WL1….M, FIG. 7C), a selector on the word line (Paragraph [0039], FIG. 11A), and at least one synthetic antiferromagnetic structure on the selector (Paragraph [0098], related to reference layer);
a plurality of second structures (having BL1….N, FIG. 7C), disposed above the first structures See FIG. 7C and 7D), extending in the second direction, and spaced apart from each other in the first direction, each of the second structures comprising a bit line crossing over a plurality of the synthetic antiferromagnetic structures in the second direction (reference layers are anti-ferromagnetic as in FIG. 11A, Paragraph [0098]), a plurality of free layers between the bit line and the synthetic antiferromagnetic structures (FIG. 11A), and a plurality of spacers on opposite sidewalls of the bit line (spacer 809 in FIG. 8), wherein the free layers (Shown in FIG. 11A, 8 as well) are disposed at an intersection where the bit line and the word line intersect (FL is at the intersection of BL and WL as shown in FIG. 10A, 10B), and the spacers comprise portions covering first sidewalls of the free layers that are opposite to each other in the first direction (FIG. 9 where FL 907 sidewall intersects Liner 921 and 923 and the portions are in opposite to each other in first direction which is horizontal direction); and
a plurality of barrier layers (as in FIG. 11A, plurality of tunnel barrier 1103 and 1113 and there are more), disposed between the first structures and the second structures, extending in the second direction, and spaced apart from each other in the first direction (FIG. 10A and 10B, Paragraph [0111]-[0114]).
However, FIG. 7A, 8, 9, 10A-10B and FIG. 11-11B are from different embodiments. The reason for using different embodiments to get to claimed invention in order to meet device functionality.
Regarding claim 2, Tran teaches the semiconductor device according to claim 1, wherein the portions of the spacers cover top surfaces of the underlying barrier layers (909 covers top surface of 905 in FIG. 9).
Regarding claim 3, Tran teaches the semiconductor device according to claim 1, wherein in each of the first structures, the number of the at least one synthetic antiferromagnetic structure is plural (The reference layer 803 can have a more complicated design that includes synthetic anti-ferromagnetic layers and additional reference layers. For simplicity, the figures and discussion omit these additional layers and focus only on the fixed magnetic layer primarily responsible for tunneling magnetoresistance in the cell as in FIG. 8 and Paragraph[0099]) and the synthetic antiferromagnetic structures are spaced apart from each other in the first direction (reference layer 1105, 1115 etc. are separated in the direction of WL).
Regarding claim 4, Tran teaches the semiconductor device according to claim 3, wherein the portions of the spacers (909) are overlapped with the barrier layers (908) and the synthetic antiferromagnetic structures (reference layer structure can partially be in third direction , not shown, but people skilled in the art should be able to achieve this without much difficulty) in a third direction perpendicular to the first direction and the second direction.
Regarding claim 5, Tran teaches the semiconductor device according to claim 3, wherein the barrier layers comprise sidewalls coplanar with sidewalls of the synthetic antiferromagnetic structures (FIG. 9, 908 and 903 sidewalls are coplanar).
Regarding claim 6, Tran teaches the semiconductor device according to claim 1, further comprising: a plurality of insulation layers, wherein each of the insulation layers is disposed below the bit line and between the free layers, and the insulation layers cover second sidewalls of the free layers that are opposite to each other in the second direction (liners goes underneath all BL and between free layers combination of FIG. 9 and 11B).
Regarding claim 7, Tran teaches a semiconductor device, comprising:
a plurality of first structures (having WL1….M, FIG. 7C), extending in a first direction (as in FIG. 7C) and spaced apart from each other in a second direction intersecting the first direction (as in FIG. 7C), each of the first structures comprising a word line (having WL1….M, FIG. 7C), a selector on the word line (Paragraph [0039], FIG. 11A), and a synthetic antiferromagnetic structure on the selector (Paragraph [0098], related to reference layer);
a plurality of second structures (having BL1….N, FIG. 7C), disposed above the first structures See FIG. 7C and 7D), extending in the second direction, and spaced apart from each other in the first direction, each of the second structures comprising a bit line crossing over a plurality of the synthetic antiferromagnetic structures in the second direction (reference layers are anti-ferromagnetic as in FIG. 11A, Paragraph [0098]) and a plurality of free layers between the bit line and the synthetic antiferromagnetic structures (FIG. 11A), and a plurality of spacers on opposite sidewalls of the bit line (spacer 809 in FIG. 8), wherein the free layers (Shown in FIG. 11A, 8 as well) are disposed at an intersection where the bit line and the word line intersect (FL is at the intersection of BL and WL as shown in FIG. 10A, 10B), and the spacers comprise portions covering first sidewalls of the free layers that are opposite to each other in the first direction (FIG. 9 where FL 907 sidewall intersects Liner 921 and 923 and the portions are in opposite to each other in first direction which is horizontal direction), wherein the free layers FL or free layer) are disposed at an intersection where the bit line and the word line intersect (FIG. 11B, 10A); and
at least one barrier layer (as in FIG. 11A, plurality of tunnel barrier 1103 and 1113 and there are more), disposed between the first structures and the second structures (FIG. 10A and 10B, Paragraph [0111]-[0114]).
However, FIG. 7A, 8, 9, 10A-10B and FIG. 11-11B are from different embodiments. The reason for using different embodiments to get to claimed invention in order to meet device functionality.
Regarding claim 8, Tran teaches the semiconductor device according to claim 7, wherein the at least one barrier layer is a continuous single film layer(1153 or 1163 is continuous single film made of Magnesium Oxide (MgO) as in Paragraph[ah [0113])).
Regarding claim 9, Tran teaches the semiconductor device according to claim 7, wherein the number of the at least one barrier layer is plural ((1153 or 1163), the barrier layers are spaced apart from each other in the first direction and the second direction, and each of the barrier layers is disposed between one of the first structures and one of the second structures (see FIG. 11B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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