Prosecution Insights
Last updated: October 02, 2026
Application No. 18/621,026

INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT TESTING METHOD

Non-Final OA §103
Filed
Mar 28, 2024
Priority
Mar 31, 2023 — TW 112112443
Examiner
MCDONNOUGH, COURTNEY G
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Realtek Semiconductor Corporation
OA Round
2 (Non-Final)
82%
Grant Probability
Favorable
2-3
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
470 granted / 576 resolved
+13.6% vs TC avg
Strong +18% interview lift
Without
With
+18.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
23 currently pending
Career history
607
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
63.3%
+23.3% vs TC avg
§102
18.6%
-21.4% vs TC avg
§112
14.6%
-25.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 576 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see pages 6-9, filed 04/02/2026, with respect to the rejection(s) of claims 1, 2-14 and 16-17 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. A new ground(s) of rejection is necessitated by the amendment. Applicant’s arguments with respect to claims 1, 2-14 and 16-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-4, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi et al. US 2003/0214316 A1 (hereinafter referred to as Maggi) in view of Ku US 2005/0054125 A1. Regarding claim 1, Maggi discloses an integrated circuit (IC) (fig. 4, elm. 112, par. [0037]), comprising: a package (fig. 4, elm. 122, par. [0037]); a target circuit (fig. 4, operating circuitry, par. [0037]); and a heating circuit (fig. 4, elm. 210, par. [0037]), configured to receive a heating signal (fig. 4, set of instructions 136 for burn-in testing the operating circuitry 118c, and instructions 138 for collecting and evaluating data, par. [0039]) and heat at least a testing portion (fig. 4, elm. 118c, par. [0037]) of the target circuit (par. [0013]) to a first predetermined temperature (par. [0007], [0031], [0038]) based on the heating signal (par. [0033], [0038]); wherein the target circuit and the heating circuit are within the package (see fig. 1-4); wherein the target circuit comprises: a first region (fig. 4, elm. 118c, par. [0037]), having a first temperature (par. [0033], [0038]); a second region (fig. 4, elm. 118a and 118b, par. [0037]), having a second temperature (par. [0033], [0038]), wherein the first temperature is higher than the second temperature; wherein the heating circuit heats (fig. 4, elm. 120, par. [0037]) the first region responding to the heating signal (par. [0039]). Maggi does not disclose explicitly a first and second temperature sensitivity. Ku discloses a first and second temperature sensitivity (fig. 4, par. [0039]-[0042]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to test heat sensitive characteristics of an IC, as taught in Ku in modifying the apparatus of Maggi. The motivation would be to accurately tests the electrical characteristics of the integrated circuit under thermal conditions such that manufacturers could precisely guarantee the temperature specification of their integrated circuits (see Ku: par. [0007]). Regarding claim 3, Maggi and Ku discloses the integrated circuit of claim 1, Maggi discloses wherein the first region is a region (fig. 4, elm. 118c, par. [0037]) which has a highest temperature sensitivity (par. [0038]) in the target circuit (fig. 4, operating circuitry, par. [0037]). Regarding claim 4, Maggi and Ku discloses the integrated circuit of claim 1, Maggi discloses wherein the heating circuit (fig.4, elm. 120, par. [0037]) comprises at least one resistor (fig. 4, electrical resistance heater, par. [0040]), wherein the heating circuit performs heating via flowing at least one current through the resistor (fig. 4, elm. 140, par. [0039]). Regarding claim 7, Kaneko discloses the integrated circuit of claim 1, wherein the heating circuit (fig. 4, elm. 120, par. [0037]) does not heat other circuits (fig. 4, elm. 118a and 118b, par. [0037]-[0038]) of the target circuit (fig. 4, operating circuitry, par. [0037]) responding to the heating signal (set of instructions 136 for burn-in testing the operating circuitry 118c, par. [0039]), wherein the other circuits are not in the testing portion (par. [0037]-[0039]). Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Ku as applied to claim 4 above, and further in view of Mimran et al. US 9,148,910 B1 (hereinafter referred to as Mimran). Regarding claim 5, Maggi and Ku discloses the integrated circuit of claim 4, Maggi and Ku do not disclose wherein the heating circuit further comprises at least one switch device, to control the flowing of the current. Mimran disclose wherein the heating circuit (fig. 1, elm. 230, col. 3, ln. 30-43) further comprises at least one switch device (fig. 1, elm. 101, col. 3, ln. 30-43), to control the flowing of the current. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a power provider switch to adjusts the current conducted by the heating element, to maintain the chip temperature to remain within a suitable temperature range, as taught in Mimran in modifying the apparatus of Maggi and Ku. The motivation would be to maintain the chip temperature to remain within a suitable temperature range. (see Mimran: col. 6, ln. 44-53). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Ku as applied to claim 1 above, and further in view of Kaneko et al. US 6,329,642 B1 (hereinafter referred to as Kaneko). Regarding claim 6, Maggi and Ku discloses the integrated circuit of claim 1, Maggi and Ku do not disclose wherein the target circuit is a clock oscillator. Kaneko discloses wherein the target circuit (fig. 2, elm. 2, col. 6, ln. 53) is a clock oscillator. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an oscillator that oscillated at a frequency depending on external temperature condition, a heater is activated when frequency of oscillator is detected to be abnormal, as taught in Kaneko in modifying the apparatus of Maggi and Ku. The motivation would be enables operating under wide operation range, irrespective of temperature conditions. (see Kaneko: col. 3, ln. 6-29). Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Ku as applied to claim 1 above, and further in view of Singh et al. WO 2018/125045 A1 (hereinafter referred to as Singh). Regarding claim 8, Maggi and Ku discloses the integrated circuit of claim 1, Maggi and Ku do not disclose wherein the heating circuit heats other circuits of the target circuit to a second predetermined temperature responding to the heating signal, wherein the other circuits are not in the testing portion, wherein the second predetermined temperature is lower than the first predetermined temperature. Singh discloses the heating circuit (fig. 1, resistors 1-N, pg. 9, ln. 1-8) heats other circuits of the target circuit to a second predetermined temperature (Nth resistor of the resistors 1-N may receive current to heat a different corresponding region 139 of the integrated circuit 110 to a second predetermined burn-in temperature, pg. 9, ln. 1-8) responding to the heating signal, wherein the other circuits are not in the testing portion, wherein the second predetermined temperature is lower than the first predetermined temperature (second predetermined burn-in temperature (e.g., a different predetermined burn-in temperature, pg. 9, ln. 1-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide resistors coupled to respective different regions of the circuitry and selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions to a predetermined burn-in temperature, as taught in Singh in modifying the apparatus of Maggi and Ku. The motivation would be targeted burn-in at the same time or in sequence may provide superior performance by reducing total burn-in time compared to whole die burn-in alone. (see Singh: pg. 8, ln. 23-29). The references are combined for the same reason already applied in the rejection of claim 8. Claim(s) 9-12 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Kinsley US 2007/0030020 A1. Regarding claim 9, Maggi discloses an IC testing method (method for performing burn-in testing of an integrated circuit, par. [0017]), for testing an IC (fig. 4, elm. 112, par. [0037]) comprising a target circuit (fig. 4, operating circuitry, par. [0037]) and a heating circuit (fig. 4, elm. 120, par. [0037]), comprising: (a) generating a heating signal (fig. 4, set of instructions 136 for burn-in testing the operating circuitry 118c, and instructions 138 for collecting and evaluating data, par. [0039]) by a testing machine (fig. 4, elm. 114, par. [0039]); (b)receiving a heating signal by the heating circuit to heat at least testing portion of the target circuit to a first predetermined temperature (par. [0007], [0031],[0038]); and (c) testing the testing portion (fig. 4, elm. 118c, par. [0037]-[0038]), by the testing machine within a predetermined time (par. [0033]) after heating the testing portion to the first predetermined temperature (par. [0005], [0033]),(clm. 13), wherein the IC testing (fig. 4, elm. 112, par. [0037]) method further comprises: testing other circuits( fig. 4, elm. 118a, 118b, par. [0037]) of the target circuit. Maggi does not disclose when a temperature of the testing portion decreases to a normal temperature, after the step (c), wherein the other circuits are not in the testing portion. Kinsley discloses the target circuit (fig. 1, elm. 100, par. [0019]-[0022]) when a temperature of the testing portion decreases to a normal temperature, after the step (c)(fig. 2, method 200, flow chart may be easily imagined for circumstances where the device will operate even if the temperature has not yet reached the desired temperature by adding a step to operate the device between 204 and 206, par. [0023]), wherein the other circuits (fig. 1, elm. 124, par. [0019]-[0020]) are not in the testing portion. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a method for pre-heating and/or maintaining a desired temperature or temperature profile in an electronic device for both testing and certain operational situations, as taught in Kinsley in modifying the apparatus of Maggi. The motivation would be maintaining a desired temperature of temperature profile in an electronic device (see Kinsley: par. [0007]). Regarding claim 10, Maggi and Kinsley discloses the IC testing method of claim 9, Maggi discloses wherein the target circuit (fig. 4, operating circuitry, par. [0037]) comprises: a first region (fig. 4, elm. 118c, par. [0037]), having a first temperature sensitivity; a second region (fig. 4, elm. 118a, 118b, par. [0037]), having a second temperature sensitivity (par. [0038]), wherein the first temperature sensitivity is higher than the second temperature sensitivity (par. [0038]); wherein the heating circuit (fig. 4, elm. 120, par. [0037]) heats the first region responding to the heating signal (fig. 4, set of instructions 136 for burn-in testing the operating circuitry 118c, and instructions 138 for collecting and evaluating data, par. [0039]). Regarding claim 11, Maggi and Kinsley discloses the IC testing method of claim 10, Maggi discloses wherein the first region (fig. 4, elm. 118c, par. [0037]) is a region which has a highest temperature sensitivity (par. [0038]) in the target circuit (fig. 4, operating circuitry, par. [0037]). Regarding claim 12, Maggi and Kinsley discloses the IC testing method of claim 9, Maggi discloses wherein the heating circuit (fig. 4, elm. 120, par. [0037]) comprises at least one resistor (fig. 4, electrical resistance heater, par. [0040]), wherein the heating circuit performs heating via flowing at least one current (fig. 4, elm. 140, par. [0040]) through the resistor. Regarding claim 16, Maggi and Kinsley discloses the IC testing method of claim 9, Maggi discloses wherein the heating circuit (fig. 4, elm. 120, par. [0037]) does not heat other circuits (fig. 4, elm. 118a and 118b, par. [0037]-[0038]) of the target circuit (fig. 4, operating circuitry, par. [0037]) responding to the heating signal (set of instructions 136 for burn-in testing the operating circuitry 118c, par. [0039]), wherein the other circuits are not in the testing portion (par. [0037]-[0039]). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Kinsley as applied to claim 12 above, and further in view of Mimran. Regarding claim 13, Maggi and Kinsley discloses the IC testing method of claim 12, Maggi and Kinsley do not disclose wherein the heating circuit further comprises at least one switch device, to control the flowing of the current. Mimran disclose the heating circuit (fig. 1, elm. 230, col. 3, ln. 30-43) further comprises at least one switch device (fig. 1, elm. 101, col. 3, ln. 30-43), to control the flowing of the current. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a power provider switch to adjusts the current conducted by the heating element, to maintain the chip temperature to remain within a suitable temperature range, as taught in Mimran in modifying the apparatus of Maggi and Kinsley. The motivation would be to maintain the chip temperature to remain within a suitable temperature range. (see Mimran: col. 6, ln. 44-53). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Kinsley as applied to claim 9 above, and further in view of Kaneko. Regarding claim 14, Maggi and Kinsley discloses the IC testing method of claim 9, Maggi and Kinsley do not disclose wherein the target circuit is a clock oscillator. Kaneko discloses wherein the target circuit (fig. 2, elm. 2, col. 6, ln. 53) is a clock oscillator. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an oscillator that oscillated at a frequency depending on external temperature condition, a heater is activated when frequency of oscillator is detected to be abnormal, as taught in Kaneko in modifying the apparatus of Maggi and Kinsley. The motivation would be enables operating under wide operation range, irrespective of temperature conditions. (see Kaneko: col. 3, ln. 6-29). Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maggi in view of Ku as applied to claim 9 above, and further in view of Singh et al. WO 2018/125045 A1 (hereinafter referred to as Singh). Regarding claim 17, Maggi and Kinsley discloses the IC testing method of claim 9, Maggi and Kinsley do not disclose wherein the heating circuit heats other circuits of the target circuit to a second predetermined temperature responding to the heating signal wherein the other circuits are not in the testing portion, wherein the second predetermined temperature is lower than the first predetermined temperature. Singh discloses the heating circuit (fig. 1, resistors 1-N, pg. 9, ln. 1-8) heats other circuits of the target circuit to a second predetermined temperature responding to the heating signal (Nth resistor of the resistors 1-N may receive current to heat a different corresponding region 139 of the integrated circuit 110 to a second predetermined burn-in temperature, pg. 9, ln. 1-8), wherein the other circuits are not in the testing portion, wherein the second predetermined temperature is lower than the first predetermined temperature (second predetermined burn-in temperature (e.g., a different predetermined burn-in temperature, pg. 9, ln. 1-8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide resistors coupled to respective different regions of the circuitry and selection circuitry to select a resistor of the resistors to receive a current to cause the selected resistor to heat a corresponding region of the regions to a predetermined burn-in temperature, as taught in Singh in modifying the apparatus of Maggi and Kinsley. The motivation would be targeted burn-in at the same time or in sequence may provide superior performance by reducing total burn-in time compared to whole die burn-in alone. (see Singh: pg. 8, ln. 23-29). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858 /FARHANA A HOQUE/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Mar 28, 2024
Application Filed
Jan 05, 2026
Non-Final Rejection mailed — §103
Apr 02, 2026
Response Filed
Aug 06, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12704545
LASER-INDUCED HOT CARRIER INJECTION (HCI) FOR ACCELERATED AGING OF INTEGRATED CIRCUITS
4y 5m to grant Granted Aug 11, 2026
Patent 12681076
HIGH VOLTAGE INTEGRATED CIRCUIT TESTING INTERFACE ASSEMBLY
5y 5m to grant Granted Jul 14, 2026
Patent 12672791
ELECTROMAGNETIC SHIELDING FOR MAGNETIC RESONANCE IMAGING METHODS AND APPARATUS
3y 0m to grant Granted Jul 07, 2026
Patent 12674767
Systems and Methods for High-Resolution Soil and Vegetation Moisture Content Monitoring using Full Polarimetric Global Navigation Satellite System (GNSS) Signals
2y 7m to grant Granted Jul 07, 2026
Patent 12656393
Methods And Systems For Measurement Of Semiconductor Structures Based On Derivative Measurement Signals
3y 0m to grant Granted Jun 16, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+18.1%)
2y 8m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 576 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month