DETAILED ACTION
This Office action is in response to the election filed 19 May 2026. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, claims 1, 5-8, 10, and 17-19, in the reply filed on 19 May 2026 is acknowledged. The traversal is on the ground(s) that the search and examination of all the claims may be made without serious burden. This is not found persuasive because the species would require a different search strategy including a different keyword search, thus resulting in serious burden if election among species were not required. Claim 7 is directed to nonelected Species III; claims 1, 5-6, 8, 10, and 17-19 are drawn to elected Species I and are examined below.
The requirement is still deemed proper and is therefore made FINAL.
Claims 2-4, 7, 9, 11-16, and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 19 May 2026.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first interconnection layer on the bottom surface of the first semiconductor substrate” (as in lines 8-9 of claim 1, and consistent with other limitations in the claim, e.g., the first interconnection layer is electrically connected to the first via vertically penetrating the first semiconductor substrate) must be shown or the feature(s) canceled from the claim(s). It appears that “the first interconnection layer” is intended to refer to layer 262 in Fig. 10, however, claim 1 recites earlier “a first semiconductor device on a bottom surface of the first semiconductor substrate” (lines 6-7) and appears to refer to the bottom surface of first semiconductor substrate 210 in Fig. 10. It is unclear how the first interconnection layer can be considered “on the bottom surface of the first semiconductor substrate,” i.e., on the bottom surface of 210, when 262 is shown on the bottom surface of 220 in Fig. 10. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-6, 8, 10, and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitations "a first semiconductor device on a bottom surface of the first semiconductor substrate" in lines 6-7 and “a first interconnection layer on the bottom surface of the first semiconductor substrate” in lines 8-9. Claim 17 similarly recites the limitations "a first semiconductor device on a bottom surface of the first semiconductor substrate" in lines 8-9 and “a first interconnection layer on the bottom surface of the first semiconductor substrate” in lines 10-11. It is unclear what is meant by “on the bottom surface of the semiconductor substrate” as recited in the above limitations.
The limitation “the first interconnection layer” appears to refer to layer 262 in Fig. 10, however, claims 1 and 17 recite earlier “a first semiconductor device on a bottom surface of the first semiconductor substrate” (at lines 6-7, lines 8-9, respectively) and appears to refer to 222 on the bottom surface of 210 (of chip 200b) in Fig. 10. Examiner notes that the entirety of 222 is not “on” the “bottom surface of the first semiconductor substrate,” rather, parts of 222 are below and above the bottom surface of 210 in Fig. 10. It is unclear how “the first interconnection layer” can be considered “on the bottom surface of the first semiconductor substrate,” i.e., on the bottom surface of 210, when 262 is shown on the bottom surface of 220 in Fig. 10. The recited “bottom surface of the first semiconductor substrate” cannot be both the bottom surface of 210 and the bottom surface of 220; thus, it is unclear and confusing as to what is meant by the recitation “on the bottom surface of the first semiconductor substrate.” For the purposes of examination, Examiner is interpreting “on” (as in the limitation “on the bottom surface of the first semiconductor substrate”) broadly, as consistent with its usage in the above claim limitations, to include elements below or above said surface and to include the presence of intervening layers.
Claims 5-6, 8, and 10 depend directly or indirectly from claim 1 and thus also contain the above indefinite language. Claims 18-19 depend directly or indirectly from claim 17 and thus also contain the above indefinite language.
Claim 6 recites the limitations “a second semiconductor device on a bottom surface of the second semiconductor substrate” in lines 3-4 and “a second interconnection layer on the bottom surface of the second semiconductor substrate” in lines 5-6. It is unclear what is meant by “on the bottom surface of the second semiconductor substrate” as recited in the above limitations.
The limitation “a second interconnection layer” appears to refer to layer 262 in Fig. 10, however, claim 6 recites earlier “a second semiconductor device on a bottom surface of the second semiconductor substrate” (at lines 3-4) and appears to refer to 222 on the bottom surface of 210 (of chip 200a) in Fig. 10. Examiner notes that the entirety of 222 is not “on” the “bottom surface of the second semiconductor substrate,” rather, parts of 222 are below and above the bottom surface of 210 in Fig. 10. It is unclear how “the second interconnection layer” can be considered “on the bottom surface of the second semiconductor substrate,” i.e., on the bottom surface of 210, when 262 is shown on the bottom surface of 220 in Fig. 10. The recited “bottom surface of the second semiconductor substrate” cannot be both the bottom surface of 210 and the bottom surface of 220; thus, it is unclear and confusing as to what is meant by the recitation “on the bottom surface of the second semiconductor substrate.” For the purposes of examination, Examiner is interpreting “on” (as in the limitation “on the bottom surface of the second semiconductor substrate”) broadly, as consistent with its usage in the above claim limitations, to include elements below or above said surface and to include the presence of intervening layers.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-6, and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0118781 A1 to Chen et al. (hereinafter “Chen”).
Regarding independent claim 1, as best understood, Chen (Figs. 8, 10) discloses a semiconductor package, comprising:
a first semiconductor chip 800 (¶ 0034; labelled in Fig. 8); and
a second semiconductor chip 700 (¶ 0035; labelled in Fig. 8) below the first semiconductor chip 800 (Fig. 10),
wherein the first semiconductor chip 800 comprises, a first semiconductor substrate 802 (¶ 0034; labelled in Fig. 8), a first semiconductor device 804 (¶ 0034) on a bottom surface of the first semiconductor substrate, a first interconnection layer 708 (¶ 0034) on the bottom surface of the first semiconductor substrate, a first via 712 (¶ 0034) vertically penetrating the first semiconductor substrate and electrically connected to the first interconnection layer 708, and a first pad 206 (¶ 0036) on a bottom surface of the first interconnection layer 708 (Fig. 10),
wherein the second semiconductor chip 700 comprises, a second semiconductor substrate 700, a second via (via under and in direct contact with 204) vertically penetrating the second semiconductor substrate (Fig. 10), and a second pad 204 (¶ 0036) on a top surface of the second semiconductor substrate and electrically connected to the second via (Fig. 10), and
wherein the first semiconductor chip 800 and the second semiconductor chip 700 are in direct contact with each other (Fig. 10), the first pad 206 and the second pad 204 include a same material and constitute a single integral object (¶ 0036; Fig. 10), the first 712 and second vias (via under and in direct contact with 204) are shifted from each other in a direction parallel to the bottom surface of the first semiconductor substrate (Fig. 10), and the first via 712 is horizontally spaced apart from the first pad 206, when viewed in a plan view (see Fig. 10), and is electrically connected to the second pad 204 through the first interconnection layer 708 (Fig. 10).
Regarding claim 5, Chen (Fig. 10) discloses the semiconductor package of claim 1, wherein a shift distance between the first 712 and second vias (via under and in direct contact with 204) is larger than half a sum of a first width of the first via 712 and a second width of the first pad 206 (Fig. 10).
Regarding claim 6, as best understood, Chen (Fig. 10) discloses the semiconductor package of claim 1, wherein the second semiconductor chip 700 further comprises: a second semiconductor device 114 (¶ 0031; labelled in Fig. 10) on a bottom surface of the second semiconductor substrate 700; and a second interconnection layer (708 under 204; ¶ 0033) on the bottom surface of the second semiconductor substrate 700, wherein the second via (via under and in direct contact with 204) connects the second interconnection layer to the second pad 204 (Fig. 10).
Regarding claim 8, Chen (Fig. 10) discloses the semiconductor package of claim 1, wherein the first via 712, the second via (via under and in direct contact with 204), the first pad 206, and the second pad 204 include a plurality of first vias, a plurality of second vias, a plurality of first pads, and a plurality of second pads, respectively, each of the first vias is electrically connected to one of the second vias through the first pad and the second pad, and each of the first pads is placed between two adjacent ones of the first vias (as is customary in the art, Fig. 10 is understood to illustrate a representative cross sectional view; thus the structures cited above include a plurality of each, as the semiconductor package comprises multiple cross sections - see, e.g., plan views of Figs. 3, 4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chen as applied to claims 1 and 8 above, and further in view of US 2019/0385966 A1 to Gao et al. (hereinafter “Gao ‘966”).
Regarding claim 10, Chen (Fig. 10) discloses the semiconductor package of claim 8, however fails to expressly disclose: wherein the first vias are arranged in a lattice shape, when viewed in a plan view, and each of the first pads is between four adjacent ones of the first vias.
In the same field of endeavor, Gao ‘966 discloses a semiconductor package including conductive interconnect components 110/302/114 (¶ 0050 - including vias 114) for bonding formed in a lattice shape when viewed in a plan view (Fig. 3B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first vias in a lattice shape as taught by Gao ‘966, for the purpose of providing conductive interconnect components for establishing electrical connection in an art recognized and conventional configuration, as exemplified by Gao ‘966 Fig. 3B. Additionally, it would have been an obvious matter of design choice to arrange each of the first pads between four adjacent ones of the first vias, since Applicant has not disclosed that each of the first pads between four adjacent ones of the first vias solves any problem or is for a particular reason. Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975).
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of US 2020/0013754 A1 to Gao et al. (hereinafter “Gao ‘754”) and Gao ‘966.
Regarding independent claim 17, as best understood, Chen (Figs. 8, 10) discloses a semiconductor package, comprising:
a first semiconductor chip 800 (¶ 0034; labelled in Fig. 8); and
a second semiconductor chip 700 (¶ 0035; labelled in Fig. 8) below the first semiconductor chip 800 (Fig. 10),
wherein the first semiconductor chip 800 comprises, a first semiconductor substrate 802 (¶ 0034; labelled in Fig. 8), a first semiconductor device 804 (¶ 0034) on a bottom surface of the first semiconductor substrate, a first interconnection layer 708 (¶ 0034) on the bottom surface of the first semiconductor substrate, a first via 712 (¶ 0034) vertically penetrating the first semiconductor substrate and electrically connected to the first interconnection layer 708, and first pads 206 (¶ 0036) on a bottom surface of the first interconnection layer 708 (as is customary in the art, Fig. 10 is understood to illustrate a representative cross sectional view; thus the semiconductor package comprises multiple cross sections and thus first pads - see, e.g., plan views of Figs. 3, 4),
wherein the second semiconductor chip 700 comprises, a second semiconductor substrate 700, a second via (via under and in direct contact with 204) vertically penetrating the second semiconductor substrate (Fig. 10), and second pads 204 (¶ 0036) on a top surface of the second semiconductor substrate (as is customary in the art, Fig. 10 is understood to illustrate a representative cross sectional view; thus the semiconductor package comprises multiple cross sections and thus second pads - see, e.g., plan views of Figs. 3, 4), and
wherein the first semiconductor chip 800 and the second semiconductor chip 700 are in direct contact with each other (Fig. 10), each of the first pads 206 and a corresponding one of the second pads 204 include a same material and constitute a single integral object (¶ 0036; Fig. 10).
Chen does not expressly disclose: a substrate; a mold layer on the substrate and enclosing the first and second semiconductor chips. In the same field of endeavor, Gao ‘754 (Fig. 17) discloses a first semiconductor chip 102 (top of stack 100; ¶ 0034) on a substrate 1702 (¶ 0078), a second semiconductor chip 102 (below top chip of stack 100; ¶ 0034) disposed below the first semiconductor chip; a mold layer 204 (¶ 0045) on the substrate 1702 and enclosing the first and second semiconductor chips (Fig. 17). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the package of Chen to include the substrate and mold layer as taught by Gao ‘754 for the purpose of forming an assembly with multiple components (¶ 0078) and providing physical protection for the first and second semiconductor chips with high heat dissipation (¶ 0045).
Chen and Gao ‘754 do not expressly disclose: the first vias are in a lattice shape, and the first pads are in a lattice shape, when viewed in a plan view, and each of the first pads is between four adjacent ones of the first vias. In the same field of endeavor, Gao ‘966 discloses a semiconductor package including conductive interconnect components 110/302/114 (¶ 0050 - including vias 114) for bonding formed in a lattice shape when viewed in a plan view (Fig. 3B). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the first vias and first pads in a lattice shape as taught by Gao ‘966, for the purpose of providing conductive interconnect components for establishing electrical connection in an art recognized and conventional configuration, as exemplified by Gao ‘966 Fig. 3B. Additionally, it would have been an obvious matter of design choice to arrange each of the first pads between four adjacent ones of the first vias, since Applicant has not disclosed that each of the first pads between four adjacent ones of the first vias solves any problem or is for a particular reason. Where the instant specification and evidence of record fail to attribute any significance (novel or unexpected results) to a particular arrangement, the particular arrangement is deemed to have been a design consideration within the skill of the art. In re Kuhle, 526 F.2d 553, 555, 188 USPQ 7, 9 (CCPA 1975).
Regarding claim 18, Chen, Gao ‘754, and Gao ‘966 disclose the semiconductor package of claim 17, Chen (Fig. 10) discloses further: wherein the first vias 712 and the second vias (via under and in direct contact with 204) are shifted from each other in a direction parallel to the bottom surface of the first semiconductor substrate (Fig. 10).
Regarding claim 19, Chen, Gao ‘754, and Gao ‘966 disclose the semiconductor package of claim 18, Chen (Fig. 10) discloses wherein the first pads 206, the second pads 204 and the second vias (via under and in direct contact with 204) are vertically aligned to each other (Fig. 10).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2020/0243466 A1 to Kim et al. disclosing a hybrid bonded semiconductor package; US 2019/0385982 A1 to Lee et al. disclosing a semiconductor package including TSV.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
25 June 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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