Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/28/2026 have been fully considered but they are not persuasive. Applicant argued that “storing test patterns in ROM is not supported by Al- Asaad. There is no mention of ROM in the cited portions of Al-Asaad or elsewhere. Additionally, and as noted above, independent claim 1 has been amended to clarify that the recited processor of the system on chip is configured to "retrieve, from a volatile memory, a scan pattern associated with a fault and defining a sequence of input signals . .. ." ROM is not the same as volatile memory. There is no indication of the amended feature in the cited portions or elsewhere of Al-Asaad. Applicant submits that this subject matter is simply missing from Al-Asaad.” The Examiner respectfully disagrees for the following reasons: The Office Action correctly identifies that Al-Asaad teaches storing and retrieving test patterns for on-line BIST. While Al-Asaad does not explicitly mention “ROM” or “volatile memory,” it teaches that test patterns are generated or stored on-chip (Fig. 1, TG; Section 3: “test patterns … generated or stored on-chip”). A person of ordinary skill would recognize that on-chip storage includes volatile memory (e.g., SRAM) as a conventional implementation. The amendment to recite “volatile memory” does not change the obviousness analysis because Al-Asaad inherently teaches the concept of retrieving test patterns from local on-chip memory during idle events (Section 5: “apply the tests to CUT while it is not being used”). Therefore, the rejection stands.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-13, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Al-Asaad et al “On-line Built-In Self-Test For Operational Faults”
Claim 1: Al-Assad teaches a system on chip (e.g. page 2: “inside a single IC- a system-on-a-chip, comprising:
a functional unit (e.g. circuit under test, CUT) having a defined functional role for the system on chip ( Section 4, “Case Study”, Figure 3); and
a processor to execute instructions for an in-field self-test (e.g. The SoC includes built-in self-test (BIST) control logic that performs on-line testing during system operation: “On-line testing requires embedding logic that continuously checks the system for correct operation. Built-in self-test (BIST) is a technique that modifies the IC by embedding test mechanisms directly into it.” Page 1, “Introduction”) that causes the processor to:
retrieve, from a memory, a scan pattern associated with a fault and defining a sequence of input signals (e.g., Figure 1, Section 3: Test pattern generator (TG) applies test sequences. TG may retrieve patterns stored on-chip. Memory type not specified, but on-chip storage (e.g., SRAM) is conventional);
apply the scan pattern to the functional unit (e.g., Al-Asaad teaches “a deterministic test sequence applied periodically to the circuit under test (CUT)… assume we have a complete test set T = {t₁, t₂,… t_q} for the set of stuck-at faults F = {f₁,… f_m}.” Each test vector tⱼ corresponds to at least one modeled fault fᵢ. The TG (test generator) applies those input sequences to the CUT- Section 3.1) during an idle event of the functional unit (e.g. The method partitions the test sequence and applies parts “separately — especially useful for real-time digital systems”, i.e., during idle cycles when the functional block is not processing user data- “Abstract);
receive an output of the functional unit in response to the scan pattern (e.g. In test mode, a test pattern generator TG applies a sequence of test patterns S to the CUT, and the test responses are evaluated by a response monitor RM.” The RM inherently receives the CUT’s output signals - On-Line Deterministic Built-in Self-Test & Fig. 1 (Generic BIST scheme)); and
output a status of the functional unit with respect to the fault based on the output of the functional unit and an expected output for the scan pattern (e.g. “The response signatures are compared with reference signatures generated or stored on-chip, and the error signal indicates any discrepancies detected.” This comparison yields a status (pass/fail) for the functional unit- Fig. 1 (RM comparison)).
Al-Asaad teaches on-chip storage generally (e.g., TG may store patterns) but does not specify volatile versus non-volatile memory. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date, to implement the on-chip storage of test patterns using volatile memory (e.g., SRAM) because:
Volatile memory (e.g., SRAM, DRAM) is a conventional, well-known storage type in system-on-chip designs.
Using volatile memory for temporary storage of test patterns during idle testing is a routine design choice that provides fast access and low power consumption during test execution.
Al-Asaad’s teaching of “stored on-chip” (Section 3, Figure 1) broadly encompasses all conventional on-chip memory types, including volatile memory.
Thus, the modification of Al-Asaad to explicitly retrieve test patterns from volatile memory would have been within the ordinary skill in the art.
Claim 2: Al-Assad teaches the system on chip of claim 1, wherein applying the scan pattern to the functional unit is in response to a self-test timer reaching a threshold amount of time while the idle event is detected (e.g. Time-triggered testing is activated at predetermined times in the operation of the system. It is often done periodically to detect permanent faults…” – pages 2-3: “Non-concurrent testing”).
Claim 3: Al-Assad teaches the system on chip of claim 1, wherein outputting the status of the functional unit with respect to the fault based on the output of the functional unit and the expected output for the scan pattern comprises: outputting a fail status in response to the output of the functional unit deviating from the expected output (e.g. “The response signatures are compared with reference signatures generated or stored on-chip, and the error signal indicates any discrepancies detected.” Fig. 1 & “Generic BIST Scheme); and outputting a pass status in response to the output of the functional unit matching the expected output (e.g. The same comparison logic inherently produces no error signal when outputs match the expected signature → pass status).
Claim 11: Al-Assad teaches a method, comprising:
detecting an idle event of a functional unit of a system on chip (e.g. testing during idle time: Section 5);
isolating the functional unit from other functional units of the system on chip in response to detecting the idle event (e.g. Isolation is inherent in non-current testing: Section 2); and
while isolating the functional unit from the other functional units of the system on chip during the idle event and responsive to a threshold amount of time having passed since completing a scan pattern self-test at the functional unit:
capturing a response of the functional unit to at least one scan pattern of a plurality of scan patterns, the at least one scan pattern having been retrieved from a memory (e.g., Figure 1, Section 3: Test pattern generator (TG) applies test sequences. TG may retrieve patterns stored on-chip. Memory type not specified, but on-chip storage (e.g., SRAM) is conventional); and
indicating a status of the functional unit with respect to a fault associated with the at least one scan pattern based on the response of the functional unit to the at least one scan pattern relative to an expected response (e.g. Response capture and status indication are core to BIST: Abstract, Section 3).
Al-Asaad teaches on-chip storage generally (e.g., TG may store patterns) but does not specify volatile versus non-volatile memory. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date, to implement the on-chip storage of test patterns using volatile memory (e.g., SRAM) because:
Volatile memory (e.g., SRAM, DRAM) is a conventional, well-known storage type in system-on-chip designs.
Using volatile memory for temporary storage of test patterns during idle testing is a routine design choice that provides fast access and low power consumption during test execution.
Al-Asaad’s teaching of “stored on-chip” (Section 3, Figure 1) broadly encompasses all conventional on-chip memory types, including volatile memory.
Thus, the modification of Al-Asaad to explicitly retrieve test patterns from volatile memory would have been within the ordinary skill in the art.
Claim 16: Al-Assad teaches a system, comprising:
a system on chip comprising an intellectual property (IP) element (e.g. CUT or MAU in Al-Asaad = IP block); and
a processor to execute instructions that cause the processor to:
detect an idle event of the IP element (e.g. testing during idle time: Section 5);
isolate the IP element from other IP elements of the system on chip in response to detecting the idle event (e.g. Isolation is inherent in non-current testing: Section 2); and
while isolating the IP element from the other IP elements of the system on chip during the idle event, perform a scan pattern self-test by:
executing at least one scan pattern of a scan pattern payload at the IP element responsive to a threshold amount of time having elapsed since previously completing the scan pattern self-test at the IP element (e.g. Threshold-based periodic testing: "time-triggered testing" (Section 2)), the scan pattern having been retrieved from a memory (e.g., Figure 1, Section 3: Test pattern generator (TG) applies test sequences. TG may retrieve patterns stored on-chip. Memory type not specified, but on-chip storage (e.g., SRAM) is conventional); and
indicating a status of the IP element with respect to a fault associated with the at least one scan pattern based on an output of the IP element to the at least one scan pattern relative to an expected output (e.g. Status indication via response checking (Abstract)).
Al-Asaad teaches on-chip storage generally (e.g., TG may store patterns) but does not specify volatile versus non-volatile memory. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date, to implement the on-chip storage of test patterns using volatile memory (e.g., SRAM) because:
Volatile memory (e.g., SRAM, DRAM) is a conventional, well-known storage type in system-on-chip designs.
Using volatile memory for temporary storage of test patterns during idle testing is a routine design choice that provides fast access and low power consumption during test execution.
Al-Asaad’s teaching of “stored on-chip” (Section 3, Figure 1) broadly encompasses all conventional on-chip memory types, including volatile memory.
Thus, the modification of Al-Asaad to explicitly retrieve test patterns from volatile memory would have been within the ordinary skill in the art.
Claim 5: Al-Assad teaches the system on chip of claim 1, wherein the in-field self-test further causes the processor to: retrieve the scan pattern from the volatile memory during the idle event of the functional unit (e.g. BIST patterns are stored or generated on-chip- Section 3 and partitioned test sequences applied during idle cycles; retrieving stored patterns is inherent to that operation: Abstract, “On-Line Testing). Not explicitly taught by Al-Assad is to copy the scan pattern from a mass storage location to the volatile memory, wherein the volatile memory is a local memory of the system on chip and the scan pattern is copied from the mass storage location by executing a scan pattern self-test application. However, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to store test patterns in accessible memory (e.g. ROM) and load them for efficient execution during idle events.
Claim 6: Al-Assad teaches the system on chip of claim 5, wherein the scan pattern self-test application is executed upon boot-up of the system on chip (e.g. BIST control can be tied to the system reset so that testing occurs during system start-up or shutdown: Section 3).
Claim 7: Al-Assad teaches the system on chip of claim 1, wherein applying the scan pattern associated with the fault to the functional unit during the idle event of the functional unit comprises: individual scan patterns of the plurality of scan patterns defining different sequences of input signals (e.g. Section 3, fig. 1); and executing the sequence of input signals by a scan controller of the system on chip (e.g. Section 4). Al-Assad uses deterministic test sequences generated by a Test Pattern Generator, which can be implemented as a counter (e.g. Section 3) but fails to teach pattern counter. However, such a modification would have been obvious to a POSITA, before the effective filing date of the claimed invention, because sequential pattern selection using counters is well-known in BIST.
Claim 8: Al-Assad teaches the system on chip of claim 7, wherein receiving the output of the functional unit in response to the scan pattern comprises recording, by the scan controller, the response of the functional unit to the sequence of input signals (e.g. the Response Monitor records and evaluates test responses: Section 3, fig. 1).
Claim 9: Al-Assad teaches the system on chip of claim 7, wherein the individual scan patterns of the plurality of scan patterns are associated with sequential numerical values, and wherein a numerical value associated with the scan pattern matches the value of the pattern counter. Al-Assad teaches that Test patterns are applied in sequence (e.g. deterministic test sets in Section 4). Thus, sequential numerical association is inherent when using a counter for pattern selection.
Claim 10: Al-Assad teaches the system on chip of claim 1, wherein the scan pattern is included in a scan pattern payload that is generated based on fault models received from a manufacturer of the system on chip (e.g. Al-Asaad shows patterns derived from fault models (stuck-at fault set F generated via ATPG, which implies that the patterns are from a manufacturer: Section 3). Al-Asaad fails to teach that the in-field self-test further causes the processor to isolate the functional unit from other functional units of the system on chip in response to detecting the idle event of the functional unit. However, Al-Asaad states, in section 2, that testing occurs when operation is “temporarily suspended,” which implies isolation . Therefore, it would have been obvious to a POSITA, before the effective filing date of the claimed invention, that non-concurrent testing isolates the CUT during testing.
Claim 12: Al-Assad teaches the method of claim 11, wherein individual scan patterns of the plurality of scan patterns are associated with sequential numerical values (e.g. Al-Assad teaches that Test patterns are applied in sequence (e.g. deterministic test sets in Section 4). Thus, sequential numerical association is inherent when using a counter for pattern selection), but fails to teach that the method further comprises: tracking execution of the plurality of scan patterns across one or more idle events of the functional unit via a pattern counter. However, Al-Assad uses deterministic test sequences generated by a Test Pattern Generator, which can be implemented as a counter (e.g. Section 3). However, such a modification would have been obvious to a POSITA, before the effective filing date of the claimed invention, because sequential pattern selection using counters is well-known in BIST.
Claim 13: Al-Assad teaches the method of claim 12, wherein tracking the execution of the plurality of scan patterns across the one or more idle events of the functional unit via the pattern counter comprises: executing the plurality of scan patterns in numerical order (e.g. Sequential test execution is inherent in deterministic BIST :Section 4).
Not explicitly taught by Al-Assad is incrementing a number value of the pattern counter after executing a scan pattern of the plurality of scan patterns at the functional unit. However, incrementing a counter is a standard implementation for sequential execution and such a modification would have been obvious to a POSITA, before the effective filing date of the claimed invention.
Claim 17: Al-Assad teaches the system of claim 16, but fails to teach that the threshold amount of time is determined based on a saturation of a self-test timer associated with the IP element, the self-test timer configured to reset upon completion of the scan pattern self-test. However, Al-Assad teaches periodic testing with bounded latency uses timers (Section 2). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to reset timers after test completion for periodic systems.
Claim 18: Al-Assad teaches the system of claim 17, wherein the completion of the scan pattern self-test comprises executing every scan pattern of the scan pattern payload over one or more idle events of the IP element (e.g. Test sequences can be partitioned and applied over multiple periods: "tests may be partitioned and interleaved" (Section 2)).
Claim 19: Al-Assad teaches the system of claim 16, but fails to teach that the instructions further cause the processor to track execution of the at least one scan pattern via a pattern counter associated with the IP element. Al-Assad uses deterministic test sequences generated by a Test Pattern Generator, which can be implemented as a counter (e.g. Section 3) but fails to teach pattern counter. However, such a modification would have been obvious to a POSITA, before the effective filing date of the claimed invention, because sequential pattern selection using counters is well-known in BIST.
Claim(s) 4, 14, and 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Al-Assad and further in view of Gizdarski (US 7,415,678 B2).
Claim 4: Al-Assad teaches the system on chip of claim 3, wherein the fail status indicates the fault is present in the functional unit (e.g. “detect the existence of fault” – Abstract), but fails to teach that the in-field self-test further causes the processor to generate an alert in response to outputting the fail status. However, Al-Assad teaches an error detection triggers corrective actions, such as reconfiguration or shutdown (see section 2). And Gizdarski teaches reporting an error alert upon fault detections errors (e.g. col. 5, lines 65-76). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporated the failure detection report of Gizdarski in the teaching of Alsaad’s for timely response.
Claim 14: Al-Assad teaches the method of claim 12, wherein capturing the response of the functional unit to the at least one scan pattern of the plurality of scan patterns comprises:
applying, by the scan controller, a series of input signals defined by the individual scan pattern to the functional unit; recording, by the scan controller, a series of output signals of the functional unit in response to the series of input signals; and after recording the series of output signals by the scan controller: exiting the idle event in response to receiving a request to execute a task at the functional unit (e.g. Testing during idle times and interrupting when tasks resume: "waiting for idle times may not be a good option... system may be briefly stopped" (Section 5) and Pattern application and response recording are standard (Section 3).
Not explicitly taught by Al-Assad is loading an individual scan pattern of the at least one scan pattern from the volatile memory storing the plurality of scan patterns to a scan controller of the system on chip or loading a subsequent individual scan pattern of the at least one scan pattern to the scan controller in response to not receiving the request to execute the task at the functional unit. However, such a technique was known in the art, before the effective filing of the claimed invention, as disclosed by Gizdarski (e.g. data store (102) and input selector (722) that loads patterns to compactor logic of SoC). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to implement teaching of Al-Assad with the one disclosed by Gizdarski in order to optimize the test.
As per claim 20, the claimed features are rejected similarly to claim 14 above. Al-Assad further teaches TG and RM handle pattern application and response recording (Section 3) and Gizdarski teaches Scan controllers and memory storage are implied (Figure 7).
Claim 15: Al-Assad teaches the method of claim 11, but fails to teach copying the plurality of scan patterns from a mass storage location to volatile memory in response to completion of a boot-up event of the system on chip, the volatile memory comprising a local memory of the system on chip; and updating the plurality of scan patterns in the mass storage location in response to receiving new fault models. However, Al-Assad teaches Boot-up testing (Section 3) and that test patterns are based on fault models (Section 3). And Gizdarski references updating test strategies (Background). Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to improve the teaching of Al-Asaad in order to update tests for improved fault coverage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 3/10/2026