Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (US 20160154590) in view of Nikoleris et al. (US 20180232313).
Regarding claim 1, FAN discloses a method (FIG. 4 method, for FIG. 9 cache memories 602 and 605 with cache controller 604, and computer readable storage medium for program to execute [0089]) comprising:
storing a variably-sized cache line into a cache, wherein a size of the variably-sized cache line is in sub-cache line sectors (FIG. 2 step 207, [0072], “Step 207: Write data, …, to a cache integrated in the processor”. FIG. 4 step 301, receiving a new memory access request that includes a memory access “granularity”, which “indicates a volume of data accessed by the memory access requests” e.g. access size in the cache line sectors, see [0063]. FAN [0004], cache lines are normally managed with granularity such as 64 bytes, however, [0047] and [0050], if data granularity is “less than a size of a cache line”, such as “8 bytes or 16 bytes”, then additional memory access need to be done, or memory access need to be combined. Thus, FAN uses access sizes that are in “sub-cache line” size/sectors. [0050] “The memory access granularity is a volume of data that is accessed by a memory access request sent by the processor, and the memory access request may be a memory access request with different granularities, such as 8 bytes or 16 bytes”);
receiving an access request for a cache that specifies an access size for the variably-sized cache line in sub-cache line sectors (FIG. 4 step 301, receiving a new memory access request that includes a memory access “granularity”, which “indicates a volume of data accessed by the memory access requests” e.g. access size in the cache line sectors, see [0063]. FAN [0004], cache lines are normally managed with granularity such as 64 bytes, however, [0047] and [0050], if data granularity is “less than a size of a cache line”, such as “8 bytes or 16 bytes”, then additional memory access need to be done, or memory access need to be combined. Thus, FAN uses access sizes that are in “sub-cache line” size/sectors. [0050] “The memory access granularity is a volume of data that is accessed by a memory access request sent by the processor, and the memory access request may be a memory access request with different granularities, such as 8 bytes or 16 bytes”); and
accessing the cache based on which sectors for the access request are present in the cache (FIG. 4 step 302, parse the memory access request and execute the memory access operation, the parsing would indicate the specific portion/sectors of the access request, see also [0070], “when receiving the memory access requests sent by the processor, the memory access requests sequentially according to the memory access request type, the base address of the memory addresses accessed by the memory access requests and the memory access granularity”, e.g. accessing the sub-cache line granularity portions based on the access requests).
Fan does not expressly teach that the cache is set-associative, or that at least one cache line of the set-associative cache has at least one sector that is resident in the cache and one sector that is not resident in the cache.
With respect to claim 1, Nikoleris teaches a set associative cache (Paragraph 0050)
Wherein at least one cache line of the set-associative cache has at least one sector that is resident in the cache and one sector that is not resident in the cache. As discussed in paragraph 0050, each physical cache line includes a plurality of sectors, and for each sector there are two bits to indicate the dirty and valid status of the sector. As discussed in paragraph 0054, when there is a cache hit, individual sectors may be invalid, showing a cache line having at least one sector that is resident in the cache (causing the cache hit) and one sector that is not in the cache (the invalid sector).
As of the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art to use a set associative cache and sector level validity tags in the system of Fan.
With respect to the cache being set-associative the rationale would have been the simple substitution of Fan’s cache with the set associative cache of Nikoleris. Fan does not disclose if the cache is direct mapped, set associative, or fully associative. Nikoleris teaches that set associative caches are known, and that the details of their use are well known enough that they don’t need to be illustrated for one of ordinary skill in the art to understand their functioning, see Nikoleris paragraph 0050, and therefore their functioning is predictable. Therefore, one of ordinary skill in the art would have been able to implement Fan’s cache as a set associative cache.
With respect to at least one cache line of the set-associative cache has at least one sector that is resident in the cache and one sector that is not resident in the cache, Nikoleris paragraph 0002 shows that the use of sector based valid and dirty tracking improves cache block utilization and reduces memory bandwidth consumption.
Therefore, it would been obvious to combine Fan and Nikoleris to obtain the invention as recited in claims 1, 10, and 19.
Regarding claim 10, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Regarding claim 19, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
Claims 2-9, 11-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fan and Nikoleris and further in view of Kaseridis et al., US Patent Application Publication Number 20240403219 (herein “KASERIDIS”), and Robinson, US Patent Application Publication Number 20240427703 (herein “ROBINSON”).
Regarding claim 2, Fan and Nikoleris teach disclose the method of claim 1,
Nikoleris further teaches that a tag for a data storage portion corresponding to the address must be found, see paragraph 0050 and 0051.
The combination of Fan and Nikoleris and does not expressly teach that the access request specifies an address that has a tag portion and a set portion.
KASERIDIS discloses wherein the access request further specifies an address that has a tag portion (FIG. 3, [0041] operation 302, “the incoming request may have a tag”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fan and Nikoleris cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Fan and Nikoleris and KASERIDIS do not explicitly disclose wherein the access request further specifies an address that has a set portion.
ROBINSON discloses wherein the access request further specifies an address that has a set portion ([0031], the PoS 110 receives a coherent request 120 from a CPU 102. [0032], “for cogran size of 64 bytes, and SFT being a 16-way associative SFT, bits 15:6 of the physical address (PA) may be used to select an SFT set”. E.g. access request with address bits for a tag portion)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Fan and Nikoleris cache access and KASERIDIS’ tag based cache access, to further include ROBINSON’s set associated cache access, to reduce penalties in terms of latency added to the memory access, interconnect bandwidth consumed for no functional benefit, and energy wasted to perform unnecessary cache lookup(s) (see ROBINSON [0024]).
Regarding claim 3, Nikoleris teaches wherein accessing the cache based on which sectors for the access request are present in the cache comprises performing a tag matching operation. Paragraph 0050 and 0051 show that a tag for a data storage portion corresponding to the address must be found.
KASERIDIS additionally discloses the method of claim 2, wherein accessing the cache based on which sectors for the access request are present in the cache comprises performing a tag matching operation (FIG. 2, [0028], “An operation 202 determines if an incoming request has arrived at the SFT for a sector match. Specifically, the incoming request may have a tag for a sector of the L2 memory that needs to be compared with the existing tags stored in the SFT entries.” E.g. tag matching by comparing the request tag to the tag in the cache).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 4, FAN and Nikoleris does not explicitly disclose the method of claim 3, wherein the tag matching operation indicates that a way corresponding to the access request is in the cache, and accessing the cache based on which sectors for the access request are present in the cache comprises comparing a valid indicator for the way to the access size.
KASERIDIS discloses the method of claim 3, wherein the tag matching operation indicates that a way corresponding to the access request is in the cache ([0043], “if there is a HIT”, “PARENT field contains a way ID of an entry”), and
accessing the cache based on which sectors for the access request are present in the cache comprises comparing a valid indicator for the way to the access size (FIG. 2, [0029]-[0032], operation 204 “enhanced tag lookup”, the access size here is assumed to be the standard granularity of the cache line at the requested address, and it is compared to tag address in the cache in the range of + sector size of the tag, see [0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 5, FAN discloses the method of claim 4, wherein the accessing includes accessing the requested sub-cache line sectors in accordance with the access request (FIG. 4 step 302, parse the memory access request and execute the memory access operation, the parsing would indicate the specific portion/sectors of the access request, see [0084]).
FAN does not explicitly disclose wherein the comparing of the valid indicator to the access size includes determining that all requested sub-cache line sectors are present in the cache.
Nikoleris paragraphs 0051 and 0054 discuss determining if all sectors are valid.
KASERIDIS discloses wherein the comparing of the valid indicator to the access size includes determining that all requested sub-cache line sectors are present in the cache ([0032], “The enhanced tag lookup finds HIT if the incoming entry is within an existing entry's sector size.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 6, FAN does not explicitly disclose the method of claim 4, wherein the comparing of the valid indicator to the access size includes determining that not all requested sub-cache line sectors are present in the cache, and the accessing includes fetching missing sub-cache line sectors into the cache.
Nikoleris paragraphs 0051 and 0054 discuss determining if all sectors are valid, and missing sectors will be retrieved from the memory.
KASERIDIS discloses the method of claim 4, wherein the comparing of the valid indicator to the access size includes determining that not all requested sub-cache line sectors are present in the cache, and the accessing includes fetching missing sub-cache line sectors into the cache ([0035]-[0037], “If none of the existing sectors covers the incoming address IN_ADDR the operation 204 determines it as a MISS.” “if the operation 216 determines that the incoming request is an allocating request, an operation 218 performs a GOBLE to find a candidate sector.” “Subsequently, an operation 220 determines if the GOBLE operation found a candidate sector. If the GOBLE operation found a candidate sector, an operation 222 updates the SFT entry metadata to reflect a new line and larger sector size.” E.g. if not all sectors covers the request, then it’s a MISS, and the cache line is allocated/fetched in the cache into candidate sector, and the tag lookup is updated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 7, FAN and Nikoleris does not explicitly disclose the method of claim 6, wherein the fetching includes identifying a data RAM and an entry for each missing sub-cache line sector, and placing the missing sub-cache line sectors into the identified data RAM and the entry.
KASERIDIS discloses the method of claim 6, wherein the fetching includes identifying a data RAM and an entry for each missing sub-cache line sector, and placing the missing sub-cache line sectors into the identified data RAM and the entry ([0035]-[0037], “If none of the existing sectors covers the incoming address IN_ADDR the operation 204 determines it as a MISS.” “if the operation 216 determines that the incoming request is an allocating request, an operation 218 performs a GOBLE to find a candidate sector.” “Subsequently, an operation 220 determines if the GOBLE operation found a candidate sector. If the GOBLE operation found a candidate sector, an operation 222 updates the SFT entry metadata to reflect a new line and larger sector size.” E.g. if not all sectors covers the request, then it’s a MISS, and the cache line is allocated/fetched in the cache RAM, and the tag lookup/entry is updated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 8, FAN and Nikoleris does not explicitly disclose the method of claim 6, wherein accessing further includes determining that no requested sub-cache line sector is present in the cache, and generating new way metadata for the access request.
KASERIDIS discloses the method of claim 6, wherein accessing further includes determining that no requested sub-cache line sector is present in the cache, and generating new way metadata for the access request ([0038], “If the GOBLE operation does not find a candidate sector, an operation 224 allocates a line as a new SFT entry with its size field set to MIN_ENTRY_SIZE.” E.g. if it’s not in the cache at all, then a new way is created as a new entry, set to minimum entry/sector size, as updated in the tag lookup metadata).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 9, FAN and Nikoleris does not explicitly disclose the method of claim 6, wherein the fetching includes evicting one or more sectors from the cache.
KASERIDIS discloses the method of claim 6, wherein the fetching includes evicting one or more sectors from the cache (FIG. 3, [0039], “operations 300 may be directed to performing line aggregations at eviction”, may evict cache tag entries by first aggregating multiple cache lines).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify FAN and Nikoleris’s cache access to further include KASERIDIS’ tag based cache access, to reduce the pressure on the system of chip (SoC) resources—specifically on-chip bandwidth and cache pipeline bandwidth (see KASERIDIS [0016]).
Regarding claim 11, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Regarding claim 12, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
Regarding claim 13, the applicant is directed to the rejections to claim 4 set forth above, as they are rejected based on the same rationale.
Regarding claim 14, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
Regarding claim 15, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
Regarding claim 16, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
Regarding claim 17, the applicant is directed to the rejections to claim 8 set forth above, as they are rejected based on the same rationale.
Regarding claim 18, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
Regarding claim 20, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
Response to Arguments
Applicant’s arguments, see the second paragraph beginning on page 6 of the remarks filed 12/15/2025, with respect to the rejection of claims 1-20 under USC 112(b) have been fully considered and are persuasive. The rejection of claims 1-20 under USC 112(b) has been withdrawn.
Applicant’s arguments, see the first paragraph beginning on page 7 of the remarks submitted 12/15/2025, with respect to the rejection(s) of claim(s) 1, 10, and 19 under 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nikoleris.
Conclusion
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/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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