DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Entry of Amendments
Claim(s) 1, 9 and 17 have been amended.
Objections to the Claims
Amendments made to claim(s) 17 have overcome the previous objections. Claim(s) 17 are no longer objected.
Rejections under 35 USC 102 and 103
Applicant’s amendments filed 05/29/2026 with respect to Claim(s) 1-21 have been fully considered but they are not persuasive.
Applicant's arguments with respect to Claim(s) 1-21 have been considered but are moot because the arguments do not apply to the reference(s) and/or ground(s) being used in the current rejection.
For further details see the rejections/objections for Claim(s) 1-21 herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-21 are rejected under 35 U.S.C. 103 as obvious over HASHIMOTO et al. (US 20120268138; hereinafter HASHIMOTO) in view of DICKEY et al. (US 20170155244).
Regarding claim 1, HASHIMOTO teaches in figure(s) 1-6 a circuit for determining characteristics of a DUT (device under test), comprising:
an inductor (inductor 46 fig. 2) coupled to a first switch (power supply switch 26);
the first switch coupled to a second switch (cutoff switch 28);
the test module comprising a DUT (DUT 200 with control section 34); and
a TVS (transient voltage suppressor) (clamp 30 known for suppressing over-voltage surge – interpreted as transient voltage suppressor/limiter) coupled to the second switch (para. 29 – clamping section that limits a voltage of a path between the inductive load section and the cutoff switch, namely a connection point A, to be within a preset range).
HASHIMOTO does not teach explicitly transient voltage suppressor; a diode coupling a test module to the first switch and the second switch.
However, Dickey teaches in figure(s) 3 transient voltage suppressor (TVS diode 360; fig. 3); a diode (diode 306, 308) coupling a test module (built-in-test circuitry 362) to the first switch (310) and the second switch (312).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of HASHIMOTO by having transient voltage suppressor; a test module coupled to the first switch and the second switch as taught by Dickey in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "TVS diode-based protection schemes that facilitate the efficient and cost effective protection of solid state power controller (SSPC) components from exposure to overvoltage conditions caused by lightning-induced pulses and other transient events, while also facilitating the efficient and cost effective incorporation of built-in-test (BIT) circuitry for TVS diode failure detection" (para. 1).
Regarding claim 2, HASHIMOTO in view of DICKEY teaches the circuit of claim 1, wherein the DUT is an eFuse (semiconductor IGBT electronic switch dut 200 of HASHIMOTO).
Regarding claim 3, HASHIMOTO in view of DICKEY teaches the circuit of claim 2, wherein the test module further comprises a discharge resistor (62.64) coupled in parallel with the eFuse (200).
Regarding claim 4, HASHIMOTO in view of DICKEY teaches the circuit of claim 3, wherein the circuit further comprises a diode (58 in para. 31 of HASHIMOTO or 306,308 in fig. 3 of DICKEY) coupled to the first switch, the second switch (312), the eFuse (200) and the discharge resistor (62,64).
Regarding claim 5, HASHIMOTO in view of DICKEY teaches the circuit of claim 4, further comprising a power supply (22) configured to apply voltage to the inductor (46).
Regarding claim 6, HASHIMOTO in view of DICKEY teaches the circuit of claim 5, wherein the TVS is configured to clamp the voltage to a predetermined level responsive to closing the second switch (para. 29 – clamping section that limits the voltage of the path between the inductive load section and the cutoff switch).
Regarding claim 7, HASHIMOTO in view of DICKEY teaches the circuit of claim 6, further comprising a controller configured to adjust timing control signals output to the first switch and the second switch to vary a DUT avalanche interval, the DUT avalanche interval comprising an interval of time between an opening of the first switch and the closing of the second switch (paras. 43-52 - when testing an avalanche breakdown voltage of the device under test, a control section turns ON or OFF the power supply switch or the cutoff switch; figs. 2-4).
Regarding claim 8, HASHIMOTO teaches in figure(s) 1-6 the circuit of claim 1, wherein the first switch and the second switch are FETs (field effect transistors) (paras. 27-28 – power supply switch and the cutoff switch are semiconductor switches such as an IGBT).
Regarding claim 9, HASHIMOTO teaches in figure(s) 1-6 a circuit for determining characteristics of a DUT (device under test) comprising:
an inductor (inductor 46 fig. 2) configured to store energy (paras. 26,47);
a first switch (power supply switch 26) coupled to the inductor and operable to provide a charging path for the inductor (para. 27);
a second switch (cutoff switch 28) coupled to the first switch, wherein the first switch and the second switch operate in concert to control a discharge of the inductor through a first discharge path (A), and the second switch is operable to provide a second discharge path (58) for the inductor responsive to tolling a DUT (DUT 200) avalanche interval (paras. 43-52 - period during which the energy accumulated in the inductive load section 24 is discharged as current is referred to as the avalanche period Tav; figs. 2-4);
a TVS (transient voltage suppressor) (clamp 30 – interpreted as transient voltage suppressor) on the second discharge path, the TVS being coupled to the second switch, wherein the energy from the inductor is diverted to the TVS responsive to the tolling of the DUT avalanche interval (paras. 29,32-33, 43-52 :- when testing an avalanche breakdown voltage of the device under test, a control section turns ON or OFF the power supply switch or the cutoff switch; figures 2-4); and
a test module (control section 34) on the first discharge path that is coupled to the first switch and the second switch, wherein the test module connects the DUT to a current output by the inductor during the DUT avalanche interval for testing current ratings (Ic fig. 4; para. 43) of the DUT.
HASHIMOTO does not teach explicitly transient voltage suppressor; a second switch coupled to the first switch without the inductor being interposed between the first switch and the second switch.
However, Dickey teaches in figure(s) 3 transient voltage suppressor (TVS diode 360; fig. 3); a second switch (312) coupled to the first switch (310) without the inductor being interposed between the first switch and the second switch.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of HASHIMOTO by having transient voltage suppressor; a second switch coupled to the first switch without the inductor being interposed between the first switch and the second switch as taught by Dickey in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "TVS diode-based protection schemes that facilitate the efficient and cost effective protection of solid state power controller (SSPC) components from exposure to overvoltage conditions caused by lightning-induced pulses and other transient events, while also facilitating the efficient and cost effective incorporation of built-in-test (BIT) circuitry for TVS diode failure detection" (para. 1).
Regarding claim 10, HASHIMOTO in view of DICKEY teaches the circuit of claim 9, wherein the DUT is an eFuse (semiconductor IGBT electronic switch dut 200 of HASHIMOTO).
Regarding claim 11, HASHIMOTO in view of DICKEY teaches the circuit of claim 10, wherein the inductor, the first switch, the second switch and the TVS are configured to apply a transient fault condition on the DUT during the DUT avalanche interval, the DUT avalanche interval comprising an interval of time between an opening of the first switch and a closing of the second switch (paras. 43-52 - when testing an avalanche breakdown voltage of the device under test, a control section turns ON or OFF the power supply switch or the cutoff switch; figs. 2-4).
Regarding claim 12, HASHIMOTO in view of DICKEY teaches the circuit of claim 11, wherein the DUT avalanche interval is adjustable based on timing control signals (para. 56 - the control section 34 switches the cutoff switch 28 from ON to OFF).
Regarding claim 13, HASHIMOTO in view of DICKEY teaches the circuit of claim 12, further comprising a controller (control 34) configured to adjust the timing control signals to vary the DUT avalanche interval.
Regarding claim 14, HASHIMOTO in view of DICKEY teaches the circuit of claim 10, wherein the TVS is configured to clamp the voltage to a predetermined level responsive to the tolling of the DUT avalanche interval (para. 29 – clamping section that limits the voltage of the path between the inductive load section and the cutoff switch).
Regarding claim 15, HASHIMOTO in view of DICKEY teaches the circuit of claim 10, wherein the current ratings for the eFuse characterize an ability of the eFuse to protect a downstream load during an overload and/or short circuit condition (para. 55 - potential Vsw at the connection point A drops due to the short circuiting of the device under test 200. If the device under test 200 malfunctions in this way, when the collector current Ic continues flowing to the device under test 200, there is a high chance that the increase of the collector current Ic will cause the device under test 200 to break down. In such a case, the control section 34 switches the cutoff switch 28 from ON to OFF).
Regarding claim 16, HASHIMOTO teaches in figure(s) 1-6 the circuit of claim 9, wherein the first switch and the second switch are FETs (field effect transistors) (paras. 27-28 – power supply switch and the cutoff switch are semiconductor switches such as an IGBT).
Regarding claim 17, HASHIMOTO teaches in figure(s) 1-6 a method for determining characteristics a DUT (device under test) comprising:
closing a first switch (power supply switch 26; fig. 2) of a circuit to pre-charge an inductor (inductor 46 fig. 2) of the circuit;
opening the first switch to discharge the inductor (step S12; fig. 5) through the DUT (DUT 200) to apply a transient fault condition for a DUT avalanche interval (paras. 43-52 - period during which the energy accumulated in the inductive load section 24 is discharged as current is referred to as the avalanche period Tav; figs. 2-4);
measuring a response of the DUT to the transient fault condition (DUT waveforms in fig. 4); and
closing a second switch (cutoff switch 28) responsive to tolling the DUT avalanche interval to divert inductor current (paras. 29,32-33, 43-52 :- when testing an avalanche breakdown voltage of the device under test, a control section turns ON or OFF the power supply switch or the cutoff switch; figures 2-4) to a TVS (transient voltage suppressor) (clamp 30– interpreted as transient voltage suppressor).
HASHIMOTO does not teach explicitly transient voltage suppressor; without the inductor coupling the first switch to the second switch.
However, Dickey teaches in figure(s) 3 transient voltage suppressor (TVS diode 360; fig. 3); without the inductor coupling the first switch (310) to the second switch (312).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of HASHIMOTO by having transient voltage suppressor; without the inductor coupling the first switch to the second switch as taught by Dickey in order to provide combining prior art elements according to known methods to yield predictable results as evidenced by "TVS diode-based protection schemes that facilitate the efficient and cost effective protection of solid state power controller (SSPC) components from exposure to overvoltage conditions caused by lightning-induced pulses and other transient events, while also facilitating the efficient and cost effective incorporation of built-in-test (BIT) circuitry for TVS diode failure detection" (para. 1).
Regarding claim 18, HASHIMOTO in view of DICKEY teaches the method of claim 17, wherein the DUT is an eFuse (semiconductor IGBT electronic switch dut 200 of HASHIMOTO).
Regarding claim 19, HASHIMOTO in view of DICKEY teaches the method of claim 18, wherein the TVS clamps a voltage across the eFuse in response to the closing of the second switch (para. 29 – clamping section that limits the voltage of the path between the inductive load section and the cutoff switch).
Regarding claim 20, HASHIMOTO teaches in figure(s) 1-6 the method of claim 17, wherein the first switch and the second switch are FETs (field effect transistors) (paras. 27-28 – power supply switch and the cutoff switch are semiconductor switches such as an IGBT).
Regarding claim 21, HASHIMOTO teaches in figure(s) 1-6 the method of claim 17, wherein a controller outputs control signals (para. 56 - the control section 34 switches the cutoff switch 28 from ON to OFF) to the first switch and the second switch to control a duration of the DUT avalanche interval (Tav).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKM ZAKARIA whose telephone number is (571)270-0664. The examiner can normally be reached on 8-5 PM (PST).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571) 272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AKM ZAKARIA/
Primary Examiner, Art Unit 2858
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