DETAILED ACTION
This communication is in response to the application filed on March 29, 2024 in which claims 1-20 are pending in the application. Claims 1, 10, and 19 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed March 29, 2024 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the security processor recited in claims 4 and 13 and the cache recit must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: display device 118 in [0015], physical function.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
[0050] recites "the security processor loads the general firmware portion 402 into memory (e.g., memory 102 or a memory of the APD 116)." Reference numeral 102 designates the processor and the memory is designated 104. The passage should recite "memory 104."
[0044] recites "the firmware executing for any given VF 204 changes when a world switch occurs." Reference numeral 204 designates the guest VMs and the virtual functions are designated 210.
[0055] recites "the VM-specific firmware 404," while element 404 is elsewhere named the VF-specific firmware portion 404 (e.g., [0046], [0053], and [0062]). Relatedly, [0009] and the abstract name the firmware portions "generic firmware portion" and "virtual function specific firmware portions," while the remainder of the specification, the claims, and Figures 4, 5A-5C, and 6 use "general firmware portion 402" and "VF-specific firmware portion 404." The nomenclature should be made consistent throughout.
The following minor typographical errors should also be corrected: [0022] recites "host virtual machine 202, is not" (extra comma); [0027] recites "an operation is performed on of for a virtual function" (should recite "on or for"); [0032] recites "included in the hypervisor instead 206" (should recite "included in the hypervisor 206 instead"); [0047] recites "the guest VMS 204" (should recite "the guest VMs 204"); [0066] recites "the auxiliary devices 106" twice in the component list.
Appropriate correction is required.
Claim Objections
Claims objected to because of the following informalities:
As per claim 1, the claim recites "A method for operating a device" in the preamble and subsequently recites "loading a general firmware portion into a device." In light of the specification, the loading step is understood to refer to the device recited in the preamble, and the step should recite “loading a general firmware portion into the device” to provide express antecedent basis. The correction also provides express antecedent for “the device” recited in claim 3.
As per claims 5 and 14, the claims recite "a virtual function-specific firmware address table," while the remaining claims hyphenate the same modifier as "virtual-function specific" (e.g., "virtual-function specific firmware portion" in claims 1, 4, 6, 8, 13, 15, and 17). The hyphenation should be made consistent.
As per claim 16, the claim recites "the processor is further configured to, prior to the world switch occurring, pre-fetching the virtual-function specific firmware portion into a cache." The word "pre-fetching" does not agree with "configured to" and should recite "pre-fetch" (compare claim 7).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 13 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 4 and 13, the claims recite "validating the virtual-function specific firmware portion by a security processor prior to loading the previously inactive virtual function into a memory" (claim 13 recites "into the memory"). It is unclear what constitutes loading a virtual function into a memory, because the specification describes a virtual function as an addressing parameter of the PCIe standard that corresponds to a logical instance of the device assigned to a virtual machine (specification as filed, paragraphs 23, 24, and 27), not as data or code that is itself loaded into a memory. The specification instead describes the security processor verifying the VF-specific firmware and loading that firmware into a memory (paragraphs 50, 51, and 62). For examination purposes, the limitation is interpreted as validating the virtual-function specific firmware portion by the security processor prior to loading the virtual-function specific firmware portion into the memory, consistent with paragraphs 51 and 62 of the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 6, 8-12, 14, 15, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US 2019/0004842) (hereinafter Jiang) in view of Fish et al. (US 2001/0042243) (hereinafter Fish).
As per claim 1, Jiang primarily teaches the invention as claimed including:
A method for operating a device, the method comprising:
for activation of a previously inactive virtual function through a world switch,
Jiang teaches that change ([0013] A switch from one VM to another is referred to as a “virtualization context switch” herein; [0045] when a virtualization context switch occurs, a microcontroller 230 stops executing firmware for the current virtual function and begins executing the firmware for the subsequent function). As described in the specification, a world switch is the change of which virtual machine or virtual function the shared device is servicing (specification as filed [0053] the command processor 136 performs a world switch, changing which VM 204 is being serviced by the APD 116).
activating a virtual-function specific firmware portion corresponding to the previously inactive virtual function ([0045] when a virtualization context switch occurs, a microcontroller 230 stops executing firmware for the current virtual function and begins executing the firmware for the subsequent function; [0051] the per-VF firmware addresses 233 correlate virtual functions with associated firmware instances ... the virtualization scheduler 236 causes the microcontroller 230 to examine the per-VF firmware addresses 233 for the address for the firmware instance associated with the subsequent virtual function and to execute that firmware; [0008] each time the virtualized device switches from performing work for a current virtual function to work for a subsequent virtual function, one or more microcontrollers of the virtualized device examines memory storing addresses for firmware for the subsequent virtual function and begins executing the firmware for that subsequent virtual function);
Jiang does not explicitly teach:
loading a general firmware portion into a device.
However, Fish teaches:
loading a general firmware portion into a device ([0021] the common firmware portions within area 102 may be accessed and executed upon every system initialization (e.g., before access/execution of any customized firmware portions), irrespective of which type of PU 12 is installed and [0018] some firmware portions may be mutually useable in common for all (or for at least a substantial portion of) the differing configurations, while other respective firmware portions may each be customized).
Jiang and Fish are both concerned with executing device firmware selected from among multiple stored firmware portions and are therefore combinable/modifiable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jiang in view of Fish because it would provide for a common firmware portion that runs for every virtual function while only the customized portions differ between functions.
Motivation would improve adaptability of the device firmware because one generically programmed component accommodates all presently known configurations instead of a fully separate firmware being maintained for each configuration as taught by Fish ([0028]).
As per claim 2, Fish further teaches wherein the general firmware portion remains activated during the activation of the previously inactive virtual function ([0026] use such resultant (i.e., determined) identification to dynamically (i.e., upon reset or initialization of the system) activate (in addition to the generic common firmware) one or more corresponding ones of the customized firmware portions and [0021] the common firmware portions within area 102 may be accessed and executed upon every system initialization ... irrespective of which type of PU 12 is installed).
As per claim 3, the combination of references above teaches wherein the general firmware portion includes operations that are common (Fish [0018] some firmware portions may be mutually useable in common for all (or for at least a substantial portion of) the differing configurations) for different virtual functions configured to execute on the device (Jiang [0045] per-VF firmware 232 is firmware for which a different version can be run for different VFs).
As per claim 5, Jiang further teaches wherein activating the virtual-function specific firmware portion comprises placing a first address into a virtual function-specific firmware address table ([0051] the per-VF firmware addresses 233 are configured, e.g., at initialization time ... to include addresses of the per-VF firmware 232. The per-VF firmware addresses 233 correlate virtual functions with associated firmware instances and [0008] the addresses for the firmware are provided by a corresponding virtual machine at configuration time).
As per claim 6, Jiang further teaches wherein activating the virtual-function specific firmware portion comprises loading the virtual-function specific firmware portion using the first address ([0051] causes the microcontroller 230 to examine the per-VF firmware addresses 233 for the address for the firmware instance associated with the subsequent virtual function and to execute that firmware and [0054] at step 506, the work-engine 117 obtains an address for firmware for a subsequent virtual function. At step 508, the work-engine 117 starts work for the subsequent virtual function, including beginning executing the firmware for the subsequent virtual function).
As per claim 8, the combination of references above teaches wherein activating the virtual-function specific firmware portion comprises replacing an old virtual-function specific firmware portion with the virtual-function specific firmware portion (Jiang [0045] a microcontroller 230 stops executing firmware for the current virtual function and begins executing the firmware for the subsequent function and [0051] the virtualization context switch also includes performing a "reset" on the work engine 117, which causes work for the current virtual function to stop in the hardware accelerator(s) 234 and microcontroller(s) 230 and causes the hardware accelerator(s) 234 and microcontroller 230 to restart) and maintaining the general firmware portion (Fish [0026] activate (in addition to the generic common firmware) one or more corresponding ones of the customized firmware portions and [0021] accessed and executed upon every system initialization).
As per claim 9, Fish further teaches wherein the activating is performed by the general firmware portion ([0022] arrangements (e.g., operations instructed by execution of the common firmware portions) which determine (e.g., during initialization) which particular type of PU 12 is installed within the system configuration, and which utilize such information to access and execute the one or ones of the customized firmware portions and [0025] execution of the common firmware portions by the PU 12 may cause the processor identifier 106 to determine identification of the PU 12).
As per claim 10, it has similar limitations as claim 1 and is therefore rejected using the same rationale. Jiang further teaches a memory; and a processor ([0009] the device 100 includes a processor 102, a memory 104, a storage 106).
As per claim 11, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 12, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 14, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 15, it has similar limitations as claim 6 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claim 8 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 9 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 1 and is therefore rejected using the same rationale. Jiang further teaches a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations ([0057] the methods or flow charts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general purpose computer or a processor).
As per claim 20, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
Claim(s) 4 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Fish in view of Zander et al. (US 2018/0089435) (hereinafter Zander).
As per claim 4, Jiang in view of Fish disclose the claimed invention as detailed above for claim 1 but do not explicitly teach:
wherein activating the virtual-function specific firmware portion includes validating the virtual-function specific firmware portion by a security processor prior to loading the previously inactive virtual function into a memory.
However, Zander teaches:
wherein activating the virtual-function specific firmware portion includes validating the virtual-function specific firmware portion by a security processor prior to loading the previously inactive virtual function into a memory ([0024] before security module 20 allows host module 40 to boot, security module 20 may validate host firmware 52. After security module 20 validates host firmware 52 security module 20 may allow host module 40 to boot ... security module 20 may store the validated host firmware 52 in SRAM 26, and security module 20 may service the read requests that host module 40 directs to embedded memory; [0025] the security module may validate the host firmware and then copy the host firmware into nonvolatile memory (NVM) in the host module before allowing the host module to boot; [0035] security coprocessor 22 may then check the integrity or validity of host firmware 52; [0033] security coprocessor 22 may hold host processor 42 and one, some, or all of the auxiliary modules in a reset state).
Jiang, Fish, and Zander are all concerned with preparing a processing device to execute the code its next task requires and are therefore combinable/modifiable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jiang in view of Fish in view of Zander because it would provide for a security coprocessor that validates each firmware image before the component that runs it is allowed to boot.
Motivation would improve security of firmware activation because only a firmware image that has passed validation is released for boot and execution as taught by Zander ([0024]).
As per claim 13, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang in view of Fish in view of Bradford et al. (US 2009/0125913) (hereinafter Bradford).
As per claim 7, Jiang in view of Fish disclose the claimed invention as detailed above for claim 1 but do not explicitly teach:
further comprising, prior to the world switch occurring, pre-fetching the virtual-function specific firmware portion into a cache.
However, Bradford teaches:
prior to the world switch occurring, pre-fetching the virtual-function specific firmware portion into a cache ([0052] initiation of a prefetch on behalf of a thread may occur prior to even the context switch to that thread; [0053] initiation of a prefetch on behalf of a thread occurs during a context switch to another thread scheduled for execution prior to that thread, e.g., immediately prior thereto ... block 70 initiates a prefetch of data and/or instructions on behalf of the next-next thread; [0019] once it is known that a context switch will be performed to a particular thread, embodiments consistent with the invention initiate prefetching of data on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory; [0050] saving the working state of the current thread being executed, including any prefetch control data as needed to indicate what data and/or instructions should be prefetched prior to resumption of execution of the thread).
Jiang, Fish, and Bradford are all concerned with a processor executing the code appropriate to its current context or configuration and are therefore combinable/modifiable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Jiang in view of Fish in view of Bradford because it would provide for a prefetch that retrieves the virtual-function specific firmware portion into the cache while the current function is still executing.
Motivation would improve resumption performance after a context switch because more of the working state is likely to be cached, or at least in the process of being retrieved into cache memory, when execution resumes as taught by Bradford ([0019]).
As per claim 16, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Forristal (US 9,081,954) discloses performing a measurement of firmware of the device using an integrity measurement logic of the device, analyzing a plurality of pointer structures of the device to determine whether a potential security violation exists (abstract), which relates to the claimed validating of the virtual-function specific firmware portion prior to loading.
Cain et al. (US 2014/0019689) discloses that a scheme referred to as a 'Region-based cache restoration prefetcher' (RECAP) is employed for cache preloading on a partition or a context switch ... and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes (abstract), which relates to the claimed pre-fetching of the virtual-function specific firmware portion into a cache.
Yoo et al. (US 9,594,687) discloses that a pre-fetcher [is] configured to perform operations including determining, for a virtual machine executing on a device ... a second virtual machine physical address for data to pre-fetch for the execution of the virtual machine on the device (abstract), which relates to the claimed pre-fetching performed for execution in a virtualized environment.
Hickey et al. (US 7,873,816) discloses that a pair of hardware threads in a multithreaded processor ... are effectively paired together, at least temporarily, to perform context switching operations such as context save and/or load operations in advance of context switches (abstract), which relates to the claimed pre-fetching prior to the world switch occurring.
Kovacevic (US 2020/0409732) discloses that virtual functions corresponding to the physical function are exposed to the guest VMs ... and the fixed function hardware block executes one of the virtual functions for one of the guest VMs based on the information stored in a corresponding one of the subsets (abstract), which relates to the claimed activation of a previously inactive virtual function on a shared processing device.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH NGO whose telephone number is (571)270-3019. The examiner can normally be reached M-F 9am to 6pm ET, first F of bi-week off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.N./ Examiner, Art Unit 2198
/PIERRE VITAL/ Supervisory Patent Examiner, Art Unit 2198
Prosecution Insights