DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species 2 in the reply filed on September 9, 2026, is acknowledged. Claim(s) 6-18 and 25-26 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species of Invention I or Invention II, there being no allowable generic or linking claim. Accordingly, claims 1-5 and 19-24 are ready for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DU et al. (US 20220122885, hereinafter “DU”).
Regarding claim 1, DU teaches in Figs. 4A-4B (shown below) and related text a semiconductor device, comprising:
a semiconductor substrate (10, Fig. 4B and ¶[0027]);
a III-N layer (12, Fig. 4B, [0027] and [0030]) over the semiconductor substrate (10, Fig. 4B), the III-N layer extending past a device region (200C, Fig. 4B and ¶[0112]) of the semiconductor substrate (10, Fig. 4B); and
a guard ring (62t1, 200t1, Figs. 4A-4B and ¶¶[0109]-[0115]) surrounding the device region (Fig. 4A), the guard ring including a discontinuity formed through the III-N layer (12, Fig. 4B) and extending into the semiconductor substrate (10, Fig. 4B).
PNG
media_image1.png
620
742
media_image1.png
Greyscale
PNG
media_image2.png
385
870
media_image2.png
Greyscale
Claim(s) 1-3, 5, 19-21, and 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (US 2022/0302296, hereinafter “Zhang”).
Regarding claim 1, Zhang teaches in Figs. 3A-3M (Figs. 3A and 3M shown below) and related text, a semiconductor device, comprising:
a semiconductor substrate (102, Fig. 3M and ¶[0028]);
a III-N layer (110, Figs. 3B, 3M, and ¶[0031]) over the semiconductor substrate (102, Fig. 3M), the III-N layer extending past a device region (204, Fig. 3A, 3M and ¶[0063]) of the semiconductor substrate (102, Fig. 3M); and
a guard ring (224, 148, 150, 152, 3A, 3M and ¶¶[0030] and [0075]) surrounding the device region (Fig. 3A), the guard ring including a discontinuity (224, 148, 150, 152, 3A, 3M and ¶¶[0030] and [0075]) formed through the III-N layer (110, Fig. 3M) and extending into the semiconductor substrate (102, Fig. 3M).
PNG
media_image3.png
542
743
media_image3.png
Greyscale
PNG
media_image4.png
480
845
media_image4.png
Greyscale
Regarding claim 2 (1), Zhang teaches wherein the discontinuity comprises a trench (224, Fig. 3M and ¶[0075]) having a metal liner (150, Fig. 3M and ¶[0061]) and filled with one or more dielectric materials (152, Fig. 3M and ¶[0061]), the metal liner formed of a first metal layer (¶[0061]).
Regarding claim 3 (2), Zhang teaches wherein the metal liner (150, Fig. 3M) includes a portion (i.e. portion of 150 extending parallel to the substrate 102, Fig. 3M) extending over a surface of a first dielectric layer (126, Fig. 3M and ¶[0043]) disposed over the III-N layer (110, Fig. 3M).
Regarding claim 5 (3), Zhang teaches wherein the guard ring includes one or more contact posts (140, Fig. 3B, 3M and ¶[0030]) through the first dielectric layer (126, Fig. 3B) and underlying the portion (Fig. 3M).
Regarding claim 19, Zhang teaches in Figs. 3A-3M (Figs. 3 A and 3M shown above) and related text, a semiconductor device, comprising:
a semiconductor substrate (102, Fig. 3M and ¶[0028]);
a III-N layer (110, Figs. 3B, 3M, and ¶[0031]) over the semiconductor substrate (102, Fig. 3M), the III-N layer extending into a device region (204, Fig. 3A, 3M and ¶[0063]) of the semiconductor substrate (102, Fig. 3M) and into a scribe lane region (206, 250, Figs. 3A, 3M, ¶¶[0063] and [0084]) of the semiconductor substrate; and
a discontinuity (224, 148, 150, 152, 3A, 3M and ¶¶[0030] and [0075]) surrounding the device region (Fig. 3A), the discontinuity formed through the III-N layer (110, Fig. 3M) and extending into the semiconductor substrate (110, Fig. 3M).
Regarding claim 20 (19), Zhang teaches wherein the discontinuity comprises a trench (224, Fig. 3M and ¶[0075[) having a metal liner (150, Fig. 3M and ¶[0061]) and filled with one or more dielectric materials (152, Fig. 3M and ¶[0061]), the metal liner formed of a first metal layer (¶[0061]).
Regarding claim 21 (20), Zhang teaches wherein the metal liner (150, Fig. 3M) includes a portion (i.e. portion of 150 extending parallel to the substrate 102, Fig. 3M) extending over a surface of a first dielectric layer (126, Fig. 3M and ¶[0043]) disposed over the III-N layer (110, Fig. 3M).
Regarding claim 23 (21), Zhang further teaches one or more contact posts (140, Fig. 3B, 3M and ¶[0030]) through the first dielectric layer (126, Fig. 3B) and underlying the portion (Fig. 3M).
Regarding claim 24 (19), Zhang teaches wherein the discontinuity comprises a trench (224, Fig. 3M and ¶[0075[) filled with one or more dielectric materials (152, Fig. 3M and ¶[0061]).
Allowable Subject Matter
Claim(s) 4 and 22 is/are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 4, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device, particularly characterized by a guard ring that includes a metal plate over a trench of the guard ring, the metal plate formed of a second metal layer and coupled to a portion of a metal liner, formed of a first metal layer and extending over a surface of a first dielectric layer disposed over a III-N layer, with one or more conductive vias through a second dielectric layer formed between the first and second metal layers, in combination with all other elements of semiconductor device recited in the claim(s). The closest prior art of record to DU et al. (US 20220122885) or Zhang et al. (US 2022/0302296) fails to disclose the above noted elements of the claim.
Regarding claim 22, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor device particularly characterized by a discontinuity surrounding a device region, where the discontinuity comprises a trench filed with a metal liner and one or more dielectric materials and includes a metal plate over the trench, the metal plate formed of a second metal layer and coupled to a portion of the metal liner, formed of a first metal layer, and extending over a surface of a first dielectric layer disposed over a III-N layer, with one or more conductive vias through a second dielectric layer formed between the first and second metal layers, in combination with all other elements of semiconductor device recited in the claim(s). The closest prior art of record to DU et al. (US 20220122885) or Zhang et al. (US 2022/0302296) fails to disclose the above noted elements of the claim.
Relevant Prior Art
The prior art of record and not relied upon is considered pertinent to applicant’s disclosure: Chang et al. (US 2019/0019770) teaches a semiconductor device that includes a semiconductor substrate, a III-N layer over the semiconductor substrate and a guard ring surrounding the device region of the semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANETA B CIESLEWICZ whose telephone number is 303-297-4232. The examiner can normally be reached M-F 8:30 AM - 2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights