DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17 in the reply filed on 7/31/26 is acknowledged.
Claims 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/31/26.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 9/05/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 9-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vinet et al. (US PGPub 2016/0013206, hereinafter referred to as “Vinet”).
Vinet discloses the semiconductor device substantially as claimed. See figures 1-17 and corresponding text, where Vinet teaches, in claim 1, a semiconductor memory device, comprising:
a first transistor (1a) and a second transistor (1b) formed in a semiconductor substrate (91) of a first conductivity type (figure 9; [0074-0096]);
an isolation trench (22, 23, 24, 25, 26) laterally separating the first transistor (1a) and the second transistor (1b);
a first dielectric layer (4) adjacent to a bottom of the isolation trench (22, 23, 24, 25, 26), wherein the first dielectric layer includes a fixed charge; and
a second dielectric (4) within a remaining portion of the isolation trench (22, 23, 24, 25, 26).
Vinet teaches, in claim 2, wherein the fixed charge includes an induced dipole charge that is located at an interface between the first dielectric layer and the second dielectric (figure 9; [0074-0096]).
Vinet teaches, in claim 3, wherein the first dielectric layer covers a bottom portion of the isolation trench (figure 9; [0074-0096]).
Vinet teaches, in claim 4, wherein the first dielectric layer is spaced apart from a bottom portion of the isolation trench by a third dielectric layer (figure 9; [0074-0096]).
Vinet teaches, in claim 5, wherein the first dielectric layer is spaced apart from a bottom and sidewalls of the isolation trench (figure 9; [0074-0096]).
Vinet teaches, in claim 9, wherein the first dielectric layer forms a direct interface with a silicon oxide layer (figure 9; [0074-0096]).
Vinet teaches, in claim 10, wherein the second dielectric layer includes silicon oxide ([0017]).
Vinet teaches, in claim 11, wherein the first and second transistors are flat transistors (figure 9; [0074-0096]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vinet et al. (US PGPub 2016/0013206, hereinafter referred to as “Vinet”) as applied to claim 1 above, and further in view of Walke et al. (US PGPub 2018/0068898, hereinafter referred to as “Walke”).
Vinet discloses the semiconductor device substantially as claimed. See the rejection above.
However, Vinet fails to explicitly teach, in claim 6, wherein the first dielectric layer includes a high-K dielectric.
Walke teaches, in claim 6, a similar device that includes gate dielectrics made with high-K dielectric materials ([0040]). In addition, Walke provides the advantages of improving efficiency, stability and reliability of semiconductor devices ([0014])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing dated of the claimed invention, to incorporate wherein the first dielectric layer includes a high-K dielectric, in the device of Vinet, according to the teachings of Walke, with the motivation of improving efficiency, stability and reliability of semiconductor devices.
Vinet fails to explicitly teach, in claim 7, wherein the high-K dielectric includes lanthanum oxide.
Walke teaches, in claim 7, a similar device that includes gate dielectrics made with high-K dielectric materials ([0040]). In addition, Walke provides the advantages of improving efficiency, stability and reliability of semiconductor devices ([0014])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing dated of the claimed invention, to incorporate wherein the high-K dielectric includes lanthanum oxide, in the device of Vinet, according to the teachings of Walke, with the motivation of improving efficiency, stability and reliability of semiconductor devices.
Vinet fails to explicitly teach, in claim 8, wherein the high-K dielectric includes hafnium oxide.
Walke teaches, in claim 8, a similar device that includes gate dielectrics made with high-K dielectric materials ([0040]). In addition, Walke provides the advantages of improving efficiency, stability and reliability of semiconductor devices ([0014])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing dated of the claimed invention, to incorporate wherein the high-K dielectric includes hafnium oxide, in the device of Vinet, according to the teachings of Walke, with the motivation of improving efficiency, stability and reliability of semiconductor devices.
Claim(s) 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vinet et al. (US PGPub 2016/0013206, hereinafter referred to as “Vinet”) in view of Walke et al. (US PGPub 2018/0068898, hereinafter referred to as “Walke”).
Vinet discloses the semiconductor device substantially as claimed. See figures 1-17 and corresponding text, where Vinet teaches, in claim 12, a semiconductor memory device, comprising:
a first transistor (1a) and a second transistor (1b) formed in a semiconductor substrate (91) of a first conductivity type;
an isolation trench (22, 23, 24, 25, 26) laterally separating the first transistor (1a) and the second transistor (1b);
a first dielectric layer adjacent to a bottom of the isolation trench, wherein the first dielectric layer includes a fixed charge; and
a second dielectric (4) within a remaining portion of the isolation trench (figure 9; [0074-0096]).
Vinet fails to teach, in claim 12, an array of memory strings;
a driver circuit coupled to the array of memory strings.
Walke teaches, in claim 12, a similar device that includes memory devices ([0061]). In addition, Walke provides the advantages of by arranging transistors in 3 dimensions (3D) instead of 2 dimensions (2D), the transistors in ICs can be placed closer to each other ([0004])
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing dated of the claimed invention, to incorporate wherein an array of memory strings; a driver circuit coupled to the array of memory strings, in the device of Vinet, according to the teachings of Walke, with the motivation of placing the transistors in ICs can be placed closer to each other.
Vinet in view of Walke teaches, in claim 13, wherein the first dielectric layer is spaced apart from a bottom portion of the isolation trench by a third dielectric layer (figure 9; [0074-0096]).
Vinet in view of Walke teaches, in claim 14, wherein the first dielectric layer is spaced apart from a bottom and sidewalls of the isolation trench (figure 9; [0074-0096]).
Vinet in view of Walke teaches, in claim 15, wherein the first dielectric layer only covers a bottom surface of the isolation trench (figure 9; [0074-0096]).
Vinet in view of Walke teaches, in claim 16, wherein the first dielectric layer covers a bottom surface and a portion of side surfaces of the isolation trench (figure 9; [0074-0096]).
Vinet in view of Walke teaches, in claim 17, wherein the array of memory strings includes NAND memory strings ([0061, Walke).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 September 30, 2026
