DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
1. This Office Action is in response to Amendment filed on date: 1/15/2026.
Claims 1-4 and 6-14 are currently pending.
Claims 1, 4, 7, 14 have been amended.
Claim 5 is cancelled.
Claim 1 is independent claim.
Response to Arguments
2. Applicant's arguments, see in pages 5-9 in the submitted Remarks, filed on 1/15/2026, with respect to the rejection on claims 1-14 have been fully considered but are moot in view of the new ground(s) of rejection.
Examiner Notes
3. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (JP2011252792; hereinafter “Yoshida”) in view of Kim et al (JP2021007149; hereinafter “Kim”) and further in view of Ono et al. (U.S. Pub. 20030155882; hereinafter “Ono”).
Regarding claim 1, Yoshida discloses a wafer test cassette (a semiconductor wafer test device 1 in Fig. 1), comprising: a first housing (a pressure vessel 10) including an O-ring 14 in Fig. 1); a second housing (a bottom plate 11) including the bottom plate 11 that is tightly attached to the pressure vessel 10 via an O-ring 14 to form an internal space 13, see Fig. 1); wherein the first housing (10) includes a probe card (a test terminals 24-25 having test electrodes 26-27, “The test device 1 can also be configured using a wafer prober” in [0015], where the wafer prober has a probe card) including at least one probe (electrodes 26-27), and the second housing (11) is configured to carry a wafer (a DUT 12 is a semiconductor wafer); wherein, when the first housing and the second housing are coupled to each other (“The pressure vessel 10 and the bottom plate 11 are in close contact with each other, thereby ensuring airtightness of the internal space 13 of the pressure vessel 10”, see [0016] and see Fig. 1), the at least one probe is configured to be in contact with at least one pad of the wafer (“When the bottom plate 11 is in close contact with the pressure vessel 10, the test object 12 placed on the mounting table 30 is positioned in the internal space 13 of the pressure vessel 10, and the electrodes 28, 29 of the test object 12 contact the test electrodes 26, 27, respectively”, see at least in [0026]); a first fluid port (a gas inlet port of a pipe 15 disposed on the vessel 10 and supplies gas into the internal space 13, see Fig. 1) disposed on the first housing or the second housing, and configured to receive an external gas (an external gas supply source 17) to the test space (13); and a gas supply device (17) having a first fluid path (15) connected to the first fluid port (see Fig. 1), the gas supply device (17) being configured to supply the external gas to the test space through the first fluid path (“The pressure vessel 10 is provided with a pipe 15 for supplying gas to the internal space 13 and a pipe 16 for exhausting gas from the internal space 13”, see [0017]); wherein after the test space receives the external gas, an air pressure value of the test space is greater than an atmospheric pressure outside the wafer test cassette (“the test voltage is supplied to the test object 12 from the test electrodes 26, 27while the air pressure in the internal space 13 of the pressure vessel 10, which serves as the test atmosphere, is increased, and the test object 12 is tested…”, see at least in [0040-41]).
Yoshida does not disclose the first housing having a first magnetic member and the second housing having a second magnetic member.
Kim discloses, in Figs. 1-3, a wafer test system (100) comprising a first housing (a probe card holder 110) having a first magnetic member (a magnetic member 155) and a second housing (a probe chuck 130) having a second magnetic member (a magnetic member 151)
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the wafer test system of Yoshida by having the first housing having a first magnetic member and the second housing having a second magnetic member as taught by Kim for purpose of providing electromagnetic force generated between the card holder and chuck by the electromagnetic force generator is increased in response to an increase in the load required to firmly contact the wafer and probe card.
Yoshida and Kim do not explicitly specify that a magnetic shielding assembly disposed in the second housing.
Ono discloses a semiconductor wafer process apparatus (100 in Fig. 1) comprising an upper housing (120) and a lower housing (126) are coupled each other, wherein a magnetic shielding assembly (a wafer table 123 may have a shielding member that shields magnetic fields, wherein the wafer table 123 is movable, see [0071-74]) disposed in the second housing (the wafer table 123 positioned in the lower housing 126, see Fig. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the wafer test system of Yoshida and Kim by having a magnetic shielding assembly disposed in the second housing as taught by Ono, for purpose of providing a shielding assembly in the wafer table so that helps to shield the stray magnetic field, so that the stray magnetic field does not affect the wafer.
Regarding claim 2, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, Yoshida further teaches wherein the external gas includes an inert gas (nitrogen gas, see [0039]).
Regarding claim 3, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, Kim further teaches wherein a magnetic attraction between the first magnetic member and the second magnetic member is determined according to the air pressure value of the test space (see at least in [0038]).
Regarding claim 4, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 3, Kim further teaches wherein the magnetic attraction between the first magnetic member and the second magnetic member increases with an increase of the air pressure value, such that a pin pressure caused by an electrical contact between the at least one probe and the at least one pad of the wafer is unchanged (see at least in [0038]).
Regarding claim 5, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, Kim further teaches wherein the first housing is magnetically connected to a test end, and the second housing is magnetically connected to a carrier seat (see Fig. 1).
Regarding claim 6, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, Yoshida further teaches comprising a switching device (18, 19 in Fig. 1) disposed between the first fluid port (15) and the gas supply device (17); wherein the switching device is configured to enable the external gas to enter the test space or release from the test space through the first fluid path (see Fig. 1 and [0019]).
Regarding claim 7, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, Yoshida further teaches comprising a second fluid port disposed on the first housing or the second housing and connected to the gas supply device; wherein the second fluid port is configured to enable the external gas to enter the test space or release from the test space (see Fig. 1 and [0017, 20]).
Regarding claim 8, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 7, wherein the gas supply device (15-20) has a second fluid path (16) connected to the second fluid port (see Fig. 1).
Regarding claim 9, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 7, wherein each of the first fluid port and the second fluid port is configured to enable the external gas to enter the test space or release from the test space, or one of the first fluid port (15) and the second fluid port (16) is configured to enable the external gas to enter the test space (by the gas inlet 15) and another of the first fluid port and the second fluid port is configured to enable the external gas to release (by the gas outlet 16) from the test space (13).
Regarding claim 10, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, wherein after a test process is performed by applying the probe card of the wafer test cassette to test the wafer, the external gas is configured to be released, and the first housing and the second housing are released from a tightly coupled state (the internal space is sealed during the test process and untight after the test process finished, see at least in [0016]).
Regarding claim 11, Yoshida and Kim and Ono disclose the wafer test cassette according to claim 1, further comprising a seal member (an O-ring 14) disposed between the first housing and the second housing and arranged around the test space (see Fig. 1).
6. Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kim and in view of Ono and further in view of Eldridge et al. (US. Pub. 2003/0122568; hereinafter “Eldridge”).
Regarding claim 12, Yoshida and Kim and Ono disclose a wafer test system (a wafer test system as shown in Fig. 1 of Yoshida), comprising: the wafer test cassette as claimed in claim 1; and a pressure transducer (22 in Fig. 1 of Yoshida) configured to detect the air pressure value of the test space (see [0022] of Yoshida).
Yoshida and Kim and Ono do not disclose a discharge transducer disposed at a side of the first housing or a side of the second housing, and configured to detect whether or not a corona discharge occurs on the at least one probe.
Eldridge discloses, in Figs. 1-4, a testing semiconductor wafer system configured monitoring a probe (probe pins 114) in a wafer test cassette (a prober 124) for a corona discharge (“a method comprising: monitoring a voltage on a power source to one of said probes; and if said voltage exceeds a predetermined threshold during a move of said stage, signaling an arc condition”, see at least in claim 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the wafer test system of Yoshida by monitoring a probe in the wafer test cassette for a corona discharge as taught by Eldridge for purpose of providing the detection of arc condition can be used to test and debug a new test program being developed to test a particular wafer.
Regarding claim 13, Yoshida and Kim and Ono and Eldridge disclose the wafer test system according to claim 12, except for explicitly specifying further comprising a control circuit correspondingly connected to the discharge transducer and the pressure transducer.
Yoshida discloses a control circuit 23 connected with the pressure sensor 22 for monitoring and controlling the internal space pressure during the test process by maintain or increase the air pressure in the internal space 13 of the pressure vessel 10 in order to reduce electrical discharge or corona discharge. Therefore, using the control circuit 23 and the pressure sensor 22 of Yoshida are electrically connected to the electrical discharge sensor 23 of Eldridge is generally recognized as being within the level skill in the art. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the wafer test system of Yoshida and Kim and Ono and Eldridge by having a control circuit correspondingly connected to the discharge transducer and the pressure transducer for purpose of preventing a dielectric breakdown may occur between the electrodes of the device under test or between the electrodes of the device under test and the test apparatus by increasing the gas pressure in the internal space when the electrical discharge is detected.
7. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Kim and in view of Ono and further in view of Eldridge.
Regarding claim 14, Yoshida and Kim and Ono discloses a wafer test method, Yoshida further teaches comprising: a detection step of detecting an air pressure value of a test space (“The pressure gauge 22 also includes a contact switch, and when it detects that the air pressure in the internal space 13 has reached a predetermined value, it transmits a detection signal to the measuring device 23”, see [0022]) in a wafer test cassette as claimed in claim 1 (see the rejection of claim 1) during a test process being performed; a monitoring step of monitoring a probe in the wafer test cassette for monitoring a pressure in the internal space during a probe test, see [0022, 33]); and a control step of maintaining or increasing the air pressure value in the test space according to a result of the monitoring step (as continue monitoring of the pressure, the air pressure in the internal space 13 of the pressure vessel 10, which serves as the test atmosphere, is maintained or increased during the test object 12 being tested. This helps to reduce electrical discharges or corona discharges between the electrodes 28, 29 of the test subject 12, or between the electrodes 28, 29 and the test electrodes 26-27. See [0040]).
Yoshida and Kim and Ono do not explicitly specify that monitoring a probe in the wafer test cassette for a corona discharge.
Eldridge discloses, in Figs. 1-4, a testing semiconductor wafer system configured monitoring a probe (probe pins 114) in a wafer test cassette (a prober 124) for a corona discharge (“a method comprising: monitoring a voltage on a power source to one of said probes; and if said voltage exceeds a predetermined threshold during a move of said stage, signaling an arc condition”, see at least in claim 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the wafer test system of Yoshida and Kim and Ono by monitoring a probe in the wafer test cassette for a corona discharge as taught by Eldridge for purpose of providing the detection of arc condition can be used to test and debug a new test program being developed to test a particular wafer.
Conclusion
8. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
1/24/2026