Prosecution Insights
Last updated: July 17, 2026
Application No. 18/622,384

DISPLAY DEVICE INCLUDING A SEMICONDUCTOR LIGHT EMITTING DEVICE

Non-Final OA §103
Filed
Mar 29, 2024
Priority
Mar 30, 2023 — RE 10-2023-0041666
Examiner
DANG, PHUC T
Art Unit
Tech Center
Assignee
LG Electronics Inc.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allowance Rate
1743 granted / 1827 resolved
+35.4% vs TC avg
Minimal +1% lift
Without
With
+1.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
33 currently pending
Career history
1851
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
86.2%
+46.2% vs TC avg
§102
5.5%
-34.5% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1827 resolved cases

Office Action

§103
CTNF 18/622,384 CTNF 77635 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Oath/Declaration 2. The oath/declaration filed on 03/29/2024 is acceptable. Priority 02-26 AIA 3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. Information Disclosure Statement 4. The office acknowledges receipt of the following items from the applicant: Information Disclosure Statement (IDS) filed on 03/29/2024 and 06/17/2025. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-21 AIA 5. Claim s 1-3, 6-7, 9-10 and 12 are rejected under 35 U.S.C. 103(a) as being unpatentable over YOUN et al., hereafter “YOUN” (U.S. Publication No. 2022/0140054 A1) in view of Kwon J (WO-2023277215-A1) . Regarding claim 1, YOUN discloses a display device including a semiconductor light emitting device comprising: a substrate (110, para [0062]); a transistor (para [0072]) disposed on the substrate (110); a barrier wall (350, para [0074]) disposed on the transistor and having an assembly hole (351, para [0074]); a semiconductor light emitting device (LED) disposed within the assembly hole (351) (Fir. 2 and para [0062]-[0074]). YOUN discloses the features of the claimed invention as discussed above, but does not disclose an insulating layer disposed on the semiconductor light emitting device and having a contact hole, and a first transparent connection electrode disposed on the insulating layer and electrically connecting the semiconductor light emitting device and the transistor, wherein the first transparent connection electrode comprises a recess pattern disposed in the contact hole. Kwon J, however, discloses an insulating layer (360) disposed on the semiconductor light emitting device (350) and having a contact hole ( opening in the insulating layer (350) ), and a first transparent connection electrode (370) disposed on the insulating layer (360) and electrically connecting the semiconductor light emitting device (350) and the transistor, wherein the first transparent connection electrode (370) comprises a recess pattern disposed in the contact hole ( opening in the insulating layer (350) ) (Fig. 10 and English Text). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of YOUN to provide an insulating layer disposed on the semiconductor light emitting device and having a contact hole, and a first transparent connection electrode disposed on the insulating layer and electrically connecting the semiconductor light emitting device and the transistor, wherein the first transparent connection electrode comprises a recess pattern disposed in the contact hole as taught by KWON J for a purpose of improving the luminous efficiency for the display device. Regarding claim 2, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein the recess pattern is disposed to contact the inner wall of the contact hole ( opening in the insulting layer (350) ) (Fig. 10 in Kwon J). Regarding claim 3, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein a depth of the contact hole ( opening in the insulting layer (350) ) is configured to correspond to a height from a bottom surface to a top surface of the first transparent connection electrode (370) (Fig. 10 in Kwon J). Regarding claim 6, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein the contact hole ( opening in the insulating layer (350) ) comprises a first contact hole disposed on a bottom surface of the contact hole and a second contact hole disposed on a side surface of the contact hole ( opening in the insulating layer (350) ); and wherein the second contact hole has a predetermined slope (Fig. 10 in Kwon J). Regarding claim 7, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein the recess pattern is disposed on the second contact hole (Fig. 10 in Kwon J). Regarding claim 9, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein a portion of the recess pattern has a slope equal to a predetermined slope of the second contact hole ( opening in the insulating layer (350) ) (Fig. 10 in Kwon J). Regarding claim 10, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein the recess pattern further comprises a second recess pattern disposed adjacent to an outside ( on top of the insulating layer (350) ) of the contact hole (opening in the insulating layer (350)) (Fig. 10 in Kwon J). Regarding claim 12, YOUN and Kwon J (citations to YOUN unless otherwise noted) discloses wherein the recess pattern is disposed adjacent to a boundary of the contact hole ( opening in the insulating layer (350) ) (Fig. 10 in Kwon J) . 07-21 AIA 6. Claim s 4-5 are rejected under 35 U.S.C. 103(a) as being unpatentable over YOUN and Kwon J in view of PARK et al., hereafter “PARK” (U.S. Publication No. 2022/0059628 A1) . Regarding claim 4, YOUN and Kwon J disclose the features of the claimed invention as discussed above, but does not disclose wherein the recess pattern comprises a plurality of pieces, and wherein the plurality of recess patterns are disposed symmetrically with respect to the contact hole. PARK, however, discloses wherein the recess pattern comprises a plurality of pieces (RME1/RME3 and RME2/RME4), and wherein the plurality of recess patterns (RME1/RME3 and RME2/RME4) are disposed symmetrically with respect to the contact hole (Fig. 26 and para [0103]). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of YOUN and Kwon J to provide wherein the recess pattern comprises a plurality of pieces, and wherein the plurality of recess patterns are disposed symmetrically with respect to the contact hole as taught by PARK for a purpose of improving mechanical stability for the display device. Regarding claim 5, YOUN, Kwon J and PARK (citations to YOUN unless otherwise noted) discloses wherein the plurality of recess patterns (RME1/RME3 and RME2/RME4) are spaced apart by the same distance from the center of the contact hole (Fig. 26 in PARK) . 07-21 AIA 7. Claim 8 is rejected under 35 U.S.C. 103(a) as being unpatentable over YOUN and Kwon J in view of Yamazaki et al., hereafter “Yamazaki” (U.S. Patent No. 8,643,921 B2) . Regarding claim 8, YOUN and Kwon J disclose the features of the claimed invention as discussed above, but does not disclose wherein the second contact hole has a curved surface. Yamazaki, however, discloses wherein the second contact hole has a curved surface (Claim 2). It would have been obvious to one having ordinary skilled in the art before the effective filing date of the claimed invention to modify the teaching of YOUN and Kwon J to provide wherein the second contact hole has a curved surface as taught by Yamazaki for a purpose of improving step coverage which forms the transparent connection electrode for the display device . Allowable Subject Matter 13-03-01 8. The following is a statement of reason for the indication of allowable subject matter: 12-151-08 AIA 07-43 12-51-08 Claim s 11 and 13-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Cited Prior Arts 07-96 AIA 9. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Kim et al. (U.S. Patent No. 11,935,986 B2) discloses a display device comprising each light emitting element LD, the first conductive semiconductor layer 11 disposed at a lower position with respect to the longitudinal direction (L) is directly coupled (or brought into direct contact) with the first electrode REL1, and the electrode layer 15 disposed thereover is directly coupled (or brought into direct contact) with the second electrode REL2. Hence, each of the light emitting elements LD in the emission area EMA of each sub-pixel may be disposed between the first electrode REL1 and the second electrode REL2 with respect to the longitudinal direction L (Fig. 6) . Conclusion 10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Phuc T. Dang whose telephone number is 571-272-1776. The examiner can normally be reached on 8:00 am-5:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHUC T DANG/Primary Examiner, Art Unit 2897 Application/Control Number: 18/622,384 Page 2 Art Unit: 2897 Application/Control Number: 18/622,384 Page 3 Art Unit: 2897 Application/Control Number: 18/622,384 Page 4 Art Unit: 2897 Application/Control Number: 18/622,384 Page 5 Art Unit: 2897 Application/Control Number: 18/622,384 Page 6 Art Unit: 2897 Application/Control Number: 18/622,384 Page 7 Art Unit: 2897 Application/Control Number: 18/622,384 Page 8 Art Unit: 2897
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Prosecution Timeline

Mar 29, 2024
Application Filed
Jun 18, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+1.3%)
1y 10m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1827 resolved cases by this examiner. Grant probability derived from career allowance rate.

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