Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is in response to the application filed on 29 March 2024. Claims 1-20 are currently pending. The rejections are as stated below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by GUO et al. (US 20230289242 A1), hereinafter “GUO”.
Regarding claims 1, 9 and 17, GUO discloses a computer-implemented method and corresponding system, comprising the steps of
directing, by a control processor, at least one shader engine to execute a first task, wherein the first task accesses a resource (abstract, ¶¶ 0052-0059 and 0189-0192); directing, by the control processor, the at least one shader engine to initiate execution of a second task, wherein the second task includes accessing the resource and wherein the at least one shader engine pauses execution of the second task before accessing the resource; (¶¶ 0052-0059, 0139-0141 and 0189-0192); receiving a signal, by the control processor, that the resource is ready after execution of the first task; and directing, by the control processor, the at least one shader engine to resume execution of the second task upon determining that the resource is ready after execution of the first task (¶¶ 0021-0023, 0049-0063, 0095-0099, 0105-0112 and 0145-0149).
Regarding claims 2, 10 and 18, GUO discloses the first task comprises writing to the resource; and the second task comprises reading from the resource (¶¶ 0201-0204 and 0169-0173).
Regarding claims 3, 11 and 19, GUO discloses the processor further performs a cache invalidation operation relating to the resource; and determining that the resource is ready after execution of the first task comprises determining that the cache invalidation operation is complete (¶¶ 0101-0104 and 0153-0155).
Regarding claims 4, 12 and 20, GUO discloses execution of the second task comprises execution of a plurality of waves; the at least one shader engine pauses execution of the second task before accessing the resource by pausing execution of each given wave in the plurality of waves before accessing the resource in the given wave; and directing the at least one shader engine to resume execution of the second task comprises directing the at least one shader engine to resume execution of the plurality of waves (¶¶ 0021-0023, 0049-0063, 0145-0149 and 0189-0192).
Regarding claims 5, 6, 13 and 14, GUO discloses the processor further executes a front-end process for the second task before determining that the resource is ready for the second task or before completion of the first task (figure 10, ¶¶ 0036-0059, 0139-0142 and 0165-0170).
Regarding claims 7, 8, 15 and 16, GUO discloses wherein a shader implementing the second task comprises a first instruction to pause the shader before a second instruction to access the resource, wherein the processor further: identifies, within a shader implementing the second task, a location of an earliest instruction to access the resource; and sets, for the shader implementing the second task, a pause point prior to the location of the earliest instruction to access the resource at which to pause execution of the shader (abstract and ¶¶ 0075-0092, 0145-0157 and 0189-0192).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
ARVO et al. US 20130155080 A1 disclose a “processing unit (48) has a shader processor (52) that executes multiple instructions in parallel. Multiple fixed function hardware units are provided to render graphics data. A command processor unit (56) is provided to receive multiple tasks from a host processor and independently schedule the multiple tasks to be selectively executed by the shader processor and the fixed function hardware units”.
Liktor et al. US 11769288 B2 discloses an "apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures … a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event".
BOURD et al. US 20180165786 A1 disclose “allocating resources of a shader processor of the GPU for a first thread of a first shader based on a first resource footprint of the first shader. The information is received from a driver identifying a second shader. The determination is made (112) on whether one or more processing elements of the shader processor are available based on the resources allocated for the first thread. A second thread of the second shader is executed (114) using the resources allocated for the first thread of the first shader on the shader processor without reconfiguring the resources allocated for the first thread of the first shader based on determination that one or more processing elements are available and the indication that the second resource footprint is smaller than the first resource footprint”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hani Kazimi whose telephone number is (571) 272-6745. The examiner can normally be reached Monday-Friday from 8:30 AM to 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abhishek Vyas can be reached on (571) 270-1836. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Respectfully Submitted
/HANI M KAZIMI/
Primary Examiner, Art Unit 3691
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