Prosecution Insights
Last updated: August 17, 2026
Application No. 18/622,823

POWER SEMICONDUCTOR DEVICE, METHOD FOR PREPARING POWER SEMICONDUCTOR DEVICE, AND ELECTRONIC APPARATUS

Non-Final OA §102
Filed
Mar 29, 2024
Priority
Sep 30, 2021 — CN 202111164572.X +1 more
Examiner
HO, ANTHONY
Art Unit
Tech Center
Assignee
Huawei Technologies Co., Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
1045 granted / 1149 resolved
+30.9% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
23 currently pending
Career history
1172
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
36.0%
-4.0% vs TC avg
§102
36.8%
-3.2% vs TC avg
§112
16.5%
-23.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1149 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group 1, claims 1-14, in the reply filed on June 29, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). Accordingly, claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 29, 2026. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on July 29, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The information disclosure statement (IDS) submitted on December 9, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. The information disclosure statement (IDS) submitted on June 18, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (CN 112951791). In re claim 1, Lin discloses a power semiconductor device, comprising: a function layer (i.e. the stack of layers 21, 4, 22, 23 is being considered as the “function layer”), wherein the function layer comprises a first area (i.e. leftmost area), a second area (i.e. rightmost area), and a third area (i.e. middle area), the third area is located between the first area and the second area, the function layer further comprises a first blocking groove (i.e. 211) provided in the third area; a first metal portion (i.e. 4), wherein the first metal portion is disposed on the first area; a second metal portion, wherein the second metal portion is disposed on the second area; an insulation layer (i.e. 22), wherein the insulation layer comprises a main body and a first blocking portion that are connected, the main body covers the first metal portion, the second metal portion, and the third area, the first blocking groove (i.e. 211) is filled with the first blocking portion, and the function layer further comprises at least one passivation layer (i.e. 23) (i.e. see at least Figures 1-4). Furthermore, the recitation “power semiconductor device” in the claim specifies an intended use or field of use and is treated as nonlimiting since it has been held that in device claims, intended use must result in a structural difference between the claim invention and the prior art in order to patentably distinguish the claim invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). In re claim 8, Lin discloses an electronic apparatus, comprising a circuit board (i.e. see at least paragraph 0044) and a power semiconductor device disposed on the circuit board, wherein a control circuit is disposed on the circuit board (i.e. it is well known in the art to have a control circuit on a circuit board in order for the circuit board to be functional), and the control circuit is configured to control turn-on and turn-off of the power semiconductor device; wherein the power semiconductor device comprising: a function layer (i.e. the stack of layers 21, 4, 22, 23 is being considered as the “function layer”), wherein the function layer comprises a first area (i.e. leftmost area), a second area (i.e. rightmost area), and a third area (i.e. middle area), the third area is located between the first area and the second area, the function layer further comprises a first blocking groove (i.e. 211) provided in the third area; a first metal portion (i.e. 4), wherein the first metal portion is disposed on the first area; a second metal portion, wherein the second metal portion is disposed on the second area; an insulation layer (i.e. 22), wherein the insulation layer comprises a main body and a first blocking portion that are connected, the main body covers the first metal portion, the second metal portion, and the third area, the first blocking groove (i.e. 211) is filled with the first blocking portion, and the function layer further comprises at least one passivation layer (i.e. 23) (i.e. see at least Figures 1-4). Furthermore, the recitation “power semiconductor device” in the claim specifies an intended use or field of use and is treated as nonlimiting since it has been held that in device claims, intended use must result in a structural difference between the claim invention and the prior art in order to patentably distinguish the claim invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). A claim containing a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Allowable Subject Matter Claims 2-7 and 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHONY HO/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 29, 2024
Application Filed
Aug 05, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
93%
With Interview (+2.4%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1149 resolved cases by this examiner. Grant probability derived from career allowance rate.

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