DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
► With respect to claim 1,
“a gate structure located on a side of the doped layer that is away from the channel layer, a side wall of the gate structure that is close to the doped layer is retracted relative to a side wall of the doped layer, and the side wall of the gate structure that is close to the doped layer is retracted relative to the side wall of the gate structure that is away from the doped layer, so that the side wall of the gate structure and the side wall of the doped layer are not in a same plane.” renders the claim indefinite. It is not clear “the side wall of the gate structure” as cited on lines 11-12 of claim 1 refers to which claimed side wall of the gate structure. Applicant is respectfully suggested to clarify and use appropriate claimed language to define scope of claim.
► With respect to claim 12,
“a gate structure located on a side of the doped layer that is away from the channel layer, a side wall of the gate structure that is close to the doped layer is retracted relative to a side wall of the doped layer, and the side wall of the gate structure that is close to the doped layer is retracted relative to the side wall of the gate structure that is away from the doped layer, so that the side wall of the gate structure and the side wall of the doped layer are not in a same plane.” renders the claim indefinite. It is not clear “the side wall of the gate structure” as cited on lines 13-14 of claim 12 refers to which claimed side wall of the gate structure. Applicant is respectfully suggested to clarify and use appropriate claimed language to define scope of claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-11, as being best understood, are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Otake et al [US 2020/0176595]
► With respect to claim 1, Otake et al (fig 1, text [0001]-[0119]) discloses the claimed semiconductor device comprising:
a channel layer (4) and a barrier layer (5) that are sequentially stacked, the channel layer being made of a group III nitride material (GaN, text [0252]), the barrier layer being made of a group III nitride material (AlGaN, text [0053]), and the barrier layer includes a gate region (fig 1);
a doped layer (21) located on a side of the barrier layer that is away from the channel layer, the doped layer being located in the gate region, and a doped layer material of the doped layer comprises a group III-V compound comprising a receptor-type doped element (acceptor doped GaN, text [0057]); and
a gate structure (23) located on a side of the doped layer that is away from the channel layer, a lower side wall of the gate structure that is close to the doped layer is retracted relative to a side wall of the doped layer, the lower side wall of the gate structure that is close to the doped layer is retracted relative to an upper side wall of the gate structure that is away from the doped layer, so that lower the side wall of the gate structure and the side wall of the doped layer are not in a same plane.
► With respect to claim 2, Otake et al discloses wherein a channel layer material of the channel layer is gallium nitride, a barrier layer material of the barrier layer is aluminum gallium nitride, and a doped layer material of the doped layer is gallium nitride or aluminum gallium nitride.
► With respect to claim 3, Otake et al (fig 1)discloses a dielectric structure (22) is disposed on a periphery of the lower side wall of the gate structure that is close to the doped layer, so that the upper side wall of the gate structure that is away from the doped layer, a side wall of the dielectric structure, and at least a part of the side wall of the doped layer are flush.
► With respect to claim 5, Otake et al (text [0058]) discloses a dielectric structure material of the dielectric structure comprises at least one of the following materials: SiO2, SiON, SiNx, AlOx, AlNx, GaOx, or TiOx.
► With respect to claim 6, Otake et al (fig 1) discloses in a plane parallel to a surface of the channel layer, the dielectric structure (22/6) surrounds the gate structure, and widths of a plurality of parts that are of the dielectric structure and that are located on different sides of the gate structure are not completely the same.
► With respect to claim 7, Otake et al (fig 1, text [0057]-[00058]) discloses a size of the dielectric structure in a direction perpendicular to the surface of the channel layer is less than 5 microns.
► With respect to claim 8, Otake et al (text [0058]-[0059]) discloses a gate structure material of the gate structure comprises at least one of the following materials: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi2, or Au.
► With respect to claim 9, Otake et al (fig 1) discloses a source (9) and a drain (10), wherein the source and the drain are located on the side of the barrier layer that is away from the channel layer, and the source and the drain are located on two sides of the gate region.
► With respect to claim 10, Otake et al (fig 1)) discloses a substrate (2), wherein the substrate is located on a side of the channel layer that is away from the barrier layer.
► With respect to claim 11, Otake et al (fig 1) discloses a buffer layer (3) located between the substrate and the channel layer.
Claims 1-5, as being best understood, is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as anticipated by Lui et al [US 2020/0212173]
► With respect to claim 1, Lui et al et al (fig 2, text [0001]-[0035]) discloses the claimed semiconductor device comprising:
a channel layer (102) and a barrier layer (104) that are sequentially stacked, the channel layer being made of a group III nitride material (GaN, text [0026]), the barrier layer being made of a group III nitride material (AlGaN, text [0026]), and the barrier layer includes a gate region (fig 2);
a doped layer (200) located on a side of the barrier layer that is away from the channel layer, the doped layer being located in the gate region, and a doped layer material of the doped layer comprises a group III-V compound comprising a receptor-type doped element (p doped GaN, text [0026]); and
a gate structure (112) located on a side of the doped layer that is away from the channel layer, a lower side wall of the gate structure that is close to the doped layer is retracted relative to a side wall of the doped layer, the lower side wall of the gate structure that is close to the doped layer is retracted relative to an upper side wall of the gate structure that is away from the doped layer, so that lower the side wall of the gate structure and the side wall of the doped layer are not in a same plane.
► With respect to claim 2, Lui et al discloses wherein a channel layer material of the channel layer is gallium nitride, a barrier layer material of the barrier layer is aluminum gallium nitride, and a doped layer material of the doped layer is gallium nitride or aluminum gallium nitride.
► With respect to claim 4 Lui et al (fig 2) discloses a dielectric structure (108) is disposed on a periphery of the side wall of the gate structure that is close to the doped layer, so that the upper side wall of the gate structure that is away from the doped layer and a side wall of the dielectric structure are flush, and at least a part of the side wall of the doped layer and the side wall of the dielectric structure are not parallel.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-14, 16-20, as being best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Otake et al [US 2020/0176595] in view of Yamada [US 2019/0157441]
► With respect to claim 12, Otake et al (fig 1, text [0001]-[0119]) discloses a semiconductor device comprising:
a channel layer (4) and a barrier layer (5) that are sequentially stacked, the channel layer being made of a group III nitride material (GaN, text [0252]), the barrier layer being made of a group III nitride material (AlGaN, text [0053]), and the barrier layer includes a gate region (fig 1);
a doped layer (21) located on a side of the barrier layer that is away from the channel layer, the doped layer being located in the gate region, and a doped layer material of the doped layer comprises a group III-V compound comprising a receptor-type doped element (acceptor doped GaN, text [0057]); and
a gate structure (23) located on a side of the doped layer that is away from the channel layer, a lower side wall of the gate structure that is close to the doped layer is retracted relative to a side wall of the doped layer, the lower side wall of the gate structure that is close to the doped layer is retracted relative to an upper side wall of the gate structure that is away from the doped layer, so that lower the side wall of the gate structure and the side wall of the doped layer are not in a same plane.
Otake et al does not expressly teach the semiconductor device is connected to a circuit board.
However, Yamada (text [0078], fig 12) teaches the semiconductor device (GaN based HEMT) is connected to the circuit board.
Therefore, it would have been obvious for those skilled in the art, in view of Yamada, to have the semiconductor device of Otake connected to the circuit board as being claimed, to provide electronic device with designed function operation as being needed.
► With respect to claim 13, Otake et al discloses wherein a channel layer material of the channel layer is gallium nitride, a barrier layer material of the barrier layer is aluminum gallium nitride, and a doped layer material of the doped layer is gallium nitride or aluminum gallium nitride.
► With respect to claim 14, Otake et al (fig 1)discloses a dielectric structure (22) is disposed on a periphery of the lower side wall of the gate structure that is close to the doped layer, so that the upper side wall of the gate structure that is away from the doped layer, a side wall of the dielectric structure, and at least a part of the side wall of the doped layer are flush.
► With respect to claim 16, Otake et al (text [0058]) discloses a dielectric structure material of the dielectric structure comprises at least one of the following materials: SiO2, SiON, SiNx, AlOx, AlNx, GaOx, or TiOx.
► With respect to claim 17, Otake et al (fig 1) discloses in a plane parallel to a surface of the channel layer, the dielectric structure (22/6) surrounds the gate structure, and widths of a plurality of parts that are of the dielectric structure and that are located on different sides of the gate structure are not completely the same.
► With respect to claim 18 , Otake et al (fig 1, text [0057]-[00058]) discloses a size of the dielectric structure in a direction perpendicular to the surface of the channel layer is less than 5 microns.
► With respect to claim 19, Otake et al (text [0058]-[0059]) discloses a gate structure material of the gate structure comprises at least one of the following materials: Ti, TiN, W, Ni, NiV, Ta, TaN, Pd, Pt, WSi2, or Au.
► With respect to claim 20, Otake et al (fig 1) discloses a source (9) and a drain (10), wherein the source and the drain are located on the side of the barrier layer that is away from the channel layer, and the source and the drain are located on two sides of the gate region.
► With respect to claim 10, Otake et al (fig 1)) discloses a substrate (2), wherein the substrate is located on a side of the channel layer that is away from the barrier layer.
► With respect to claim 11, Otake et al (fig 1) discloses a buffer layer (3) located between the substrate and the channel layer.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Otake et al [US 2020/0176595] in view of Liu et al [US 2020/02121073]
► With respect to claim 4, Otake et al substantially disclose the claimed semiconductor device comprising a dielectric structure (22) is disposed on a periphery of the lower side wall of the gate structure that is close to the doped layer, so that the upper side wall of the gate structure that is away from the doped layer and a side wall of the dielectric structure are flush. Otake et al does not expressly teach at least a part of the side wall of the doped layer and the side wall of the dielectric structure are not parallel.
However, Liu et al (fig 2, text [0030]-[0031]) teaches at least a part of the side wall of the doped layer (200) and the side wall of the dielectric structure (108) by having an area of a bottom portion (200b) of the doped layer (200) greater than an area of the top portion (200a) of the doped layer (200).
Therefore, it would have been obvious for those skilled in the art to modify the semiconductor device of Otake et al by having the part of the side wall of the doped layer and the side wall of the dielectric structure being not parallel as being claimed, per taught by Liu et al, to provide an improved semiconductor device with reduced leakage path in HEMT device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Otake et al [US 2020/0176595] in view of Yamada [US 2019/0157441] as applied to claim 12 above, in further view of Liu et al [US 2020/02121073]
► With respect to claim 15, Otake et al in view of Yamada substantially disclose the claimed electronic device comprising a dielectric structure is disposed on a periphery of the lower side wall of the gate structure that is close to the doped layer, so that the upper side wall of the gate structure that is away from the doped layer and a side wall of the dielectric structure are flush. Otake et al does not expressly teach at least a part of the side wall of the doped layer and the side wall of the dielectric structure are not parallel.
However, Liu et al (fig 2, text [0030]-[0031]) teaches at least a part of the side wall of the doped layer (200) and the side wall of the dielectric structure (108) by having an area of a bottom portion (200b) of the doped layer (200) greater than an area of the top portion (200a) of the doped layer (200).
Therefore, it would have been obvious for those skilled in the art to modify the electronic device of Otake et al in view of Yamada by having the part of the side wall of the doped layer and the side wall of the dielectric structure being not parallel as being claimed, per taught by Liu et al, to provide an improved electronic device with reduced gate leakage problem.
Conclusion
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812
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