DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 6, 8 – 11, 13, 15, 17, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pat Pub 2020/0210831) in view of Liu et al. (US Pat Pub 2022/334737) or Sheperek et al. (US Pat Pub 2022/059181).
Fu et al. (US Pat Pub 2013/0145199): powering off and powering on.
Regarding claims 1, 9 and 15, Zhang et al. disclose a method (see for example figs. 1 – 13 and all related texts, particularly figs. 5 – 2, para 0051 – 0066) performed by a controller (620 in fig. 12, para 0054 – 0057, 0070) of a solid-state drive (SSD) (storage device 1200 in fig. 12, para 0070), the method comprising:
performing, on one or more blocks of a non-volatile memory device of the SSD, read operations using pre-determined threshold voltages associated with two overlapped charge states (operations 910, 920 in fig. 9, para 0064, with possibly overlapping neighboring states as shown in fig. 5, para 0051 – 0052);
determining, using a machine learning model, a change in threshold voltages associated with the two overlapped charge states (operation 950 of fig. 9, para 0064),
wherein the machine learning model determines the change in threshold voltages using bit error rates associated with the read operations (caused by retention/endurance/read disturb inputs in neural network of fig. 7, para 0059 – 0060),
wherein the machine learning model is trained using characterization data that identifies different changes in threshold voltages for different data retention conditions for the two overlapped charge states of one or more non-volatile memory devices (710 in fig. 7, para 0059 – 0060), and
wherein the machine learning model is trained to determine changes in threshold voltages for the two overlapped charge states (operation 1020 in fig. 10, para 0066); and
determining adjusted threshold voltages associated with the two overlapped charge states based on the change in threshold voltages (operation 1040 in fig. 10, para 0066),
wherein subsequent read operations are performed on the one or more blocks using the adjusted threshold voltages (operation 1040 in fig. 10, para 0066).
Zhang et al. disclose the method as set forth above, except wherein the read operations are performed after a power-on condition following a power-off condition on the non-volatile memory device, and other related steps performed after the power-off condition as further claimed in claim 1, for which the shift of threshold voltages due to a power-off condition is corrected (as discussed in para 0020 of the instant specification).
However, the feature in which triggering the determination of threshold voltage shifts after a power off condition is universally adapted in the state of the art for solving the same problem. See for example fig. 4, para 0069 – 0074 of Liu et al. (737’ reference) or fig. 6, para 0053, 0065 of Sheperek et al. (181’ reference).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention to combine the references as cited, so that machine learning algorithm to determine the change in threshold voltages after a power-off condition, so that the machine learning model operates in continuous manner.
Regarding claims 2, 10 and 20, Zhang et al. also disclose a neural network implementation of the machine learning model (fig. 7, para 0059) in which program/erase cycles with different data retention conditions are identified within the characterization data (as information stored in the die indices, block indices, and word line indices, see para 0054).
Regarding claims 5, 13 and 17, Zhang in view of Liu further disclose
performing for a block of memory of the nonvolatile memory, additional read operations to determine threshold voltages associated with the two overlapped charge states (334 of fig. 3, see also para 0061);
determining a health of the block based on the additional read operations and the change in threshold voltages associated with the two overlapped charge states (336 – 337 of fig. 3, and para 0064); and
determining, based on the health of the block, a period of time for performing a refresh operation on the block (338 of fig. 3, para 0065 – 0068).
Therefore, it would have been obvious to one of ordinary skill in the art, to combine the features taught by the references as cited in order to provide an implementation of a block refresh operation.
Regarding claims 6, 11 and 19, Zhang in view of Liu/Sheperek further disclose performing a lookup operation on a data structure, based on the change in threshold voltages, to determine threshold voltages of other charge states after the power-off condition.
Sheperek et al. disclose the use of a look-up data structure (metadata tables 210 in fig. 2) based on the change of one charge state to determine threshold voltages of other charge states (e.g. Q8, para 0072).
Therefore, it would have been obvious to one of ordinary kill in the art, before the effective filing date of the invention, to combine the references as cited in order to provide an alternative for generating the threshold voltages of other charge states given the determination of one charge state.
Regarding claim 8, Zhang et al. in view of Sheperek also disclose the use of the highest state for performing the read operations (highest charge state Q8, para 0072).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the references as cited, in order to choose the most vulnerable state as a read threshold to determine the adjusted threshold voltages.
Claim(s) 3, 4, 14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pat Pub 2020/0210831) in view of Liu et al. (US Pat Pub 2022/334737) or Sheperek et al. (US Pat Pub 2022/059181), and further in view of Sharifi et al. (US Pat Pub 2023/097679).
Regarding claims 3, 14 and 16, Zhang and Liu/Sheperek disclose the limitations set forth above, except analyzing Program/erase information identifying dates and times of P/E cycles of a plurality of blocks of the non-volatile memory device and identifying the one or more blocks as blocks of the plurality of blocks with most recent program/erase cycles based on analyzing the P/E information (claims 3, 14 and 16).
However, Sharifi et al. disclose identification of dates and time of P/E timestamps (para 0048) and identifying the blocks with the most recent P/E operations (operations 804, 806 in fig. 8, para 0098, 0099, wherein blocks are sorted based on this information and therefore said blocks are identified through the result of the sorting).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts as cited, in order to provide indication of the most recent P/E blocks for tracking purposes.
Regarding claim 4, Zhang in view of Liu/Sheperek fail to further disclose performing P/E cycles on the one or more blocks prior to the power-off condition; storing, prior to the power-off condition, P/E information indicating that the program/erase cycles were performed on the one or more blocks; obtaining the program/erase information after the power-off condition; and identifying the one or more blocks based on the P/E information.
However, Sharifi discloses obtaining the P/E information of blocks after the power-off condition (operation 802, fig. 8, para 0097).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the references as cited, in order to provide indication of the P/E status of the blocks after the power-off condition for tracking purposes.
Claim(s) 7, 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US Pat Pub 2020/0210831) in view of Liu et al. (US Pat Pub 2022/334737) or Sheperek et al. (US Pat Pub 2022/059181), and further in view of Miladinovic (US Pat pub 2019/172542).
Regarding claims 7, 12 and 18, Zhang in view of Liu/Sheperek fail to further disclose performing a mathematical operation, using the change in threshold voltages, to determine threshold voltages of other charge states after the power-off condition.
Miladinovic discloses using mathematical operation in the form of theoretical calculations to extrapolate threshold voltages of other charges states (710 in fig. 7, para 0183).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the references as cited, to provide an alternative for generating the threshold voltages of other charge states given the determination of one charge state.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention.
Fu et al. (US Pat Pub 2013/0145199), para 0049, 0050, fig. 2a, memory read after power disconnected.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 May 19, 2026
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