DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 6, 8, 15, 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, species, and subspecies, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/28/2026.
Claim Objections
Claim 9 is/are objected to because of the following informalities:
Claim 9 recites “the same material” in Line L2 but should read –a same material--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 5, 7 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ko et al. (US20250054822A1-Ko22).
Regarding claim 1, Ko22 discloses a semiconductor structure (integrated structure with semiconductor substrate-Abstract) comprising:
a first source drain (First source drain 130 having a front side /top side and a backside / bottom side-Examiner's annotated Fig 9B) having
a frontside (First source drain 130 having a front side /top side and a backside / bottom side-Examiner's annotated Fig 9B)and
a backside (First source drain 130 having a front side /top side and a backside / bottom side-Examiner's annotated Fig 9B);
a two-stage backside contact (Two-stage backside contact BDC/MPR4-Examiner's annotated Fig 9B) having
an upper portion (Upper portion DBC of two-stage backside contact, contacting the backside / bottom side of first source drain 130-Examiner's annotated Fig 9B) and
a lower portion (Lower portion MPR4 of two-stage backside contact, contacting Backside first metal line MN2-Examiner's annotated Fig 9B); and
a backside first metal line (Examiner's annotated Fig 9B);
wherein the upper portion contacts the backside of the first source drain (Upper portion DBC of two-stage backside contact, contacting the backside / bottom side of first source drain 130-Examiner's annotated Fig 9B) and
the lower portion contacts the backside first metal line (Lower portion MPR4 of two-stage backside contact, contacting Backside first metal line MN2-Examiner's annotated Fig 9B).
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Regarding claim 2, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 further discloses a semiconductor structure
wherein the upper portion has a largest width that is less than a largest width of the lower portion (Upper portion DBC having largest width being less than a largest width of lower portion MPR4 as indicated by continuous lines-Examiner's annotated Fig 9B).
Regarding claim 3, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 further discloses a semiconductor structure
wherein the upper portion has a largest width that is less than a smallest width of the lower portion (Upper portion DBC having largest width being less than a smallest width of lower portion MPR4 as indicated by continuous lines-Examiner's annotated Fig 9B).
Regarding claim 5, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 further discloses a semiconductor structure further comprising
a second source drain having a backside (Second source drain 130 having a backside / Right side-Examiner's annotated Fig 8C),
wherein the upper portion contacts the backside of the second source drain (Upper portion VPR of two-stage backside contact, electrically contacting so contacting the backside / Left side of first source drain 130 and Second source drain 130 backside / Right side-Examiner's annotated Fig 8C, [0099] L1-25).
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Regarding claim 7, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 further discloses a semiconductor structure
wherein the upper portion is laterally centered with respect to the lower portion (Upper portion VPR being laterally centered with respect to lower portion MPR as indicated by dashed lines-Examiner's annotated Fig 8C).
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al. (US 20210384106 A1-Do06).
Regarding claim 10, Do06 discloses a semiconductor structure (Stacked integrated circuit device with upper transistor and lower transistor so a semiconductor structure -Abstract) comprising:
a bottom source drain (bottom source drain 26_L1-Fig 2B);
a top source drain located above the bottom source drain (top source drain 26_U1 located above bottom source drain 26_L1-Fig 2B),
wherein the top source drain has a backside (top source drain 26_U1 having a backside/ Bottom side-Fig 2B);
a two-stage backside contact (a two-stage backside contact-28/30-Fig 2B) having
an upper portion (Upper portion 28-Fig 2B) and
a lower portion (Lower portion-Fig 2B); and
a backside first metal line (Backside first metal line P2-Fig 2B);
wherein the upper portion contacts the backside of the top source drain (upper portion 28 contacting backside /Bottom side of the top source drain 26_U1-Fig 2B) and
the lower portion contacts the backside first metal line (lower portion 30 contacting backside first metal line P2-Fig 2B).
Claim(s) 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smith et al. (US 20240047342 A1-Smith42).
Regarding claim 21, Smith42 discloses an integrated circuit ([0003] L1-3) comprising:
a source drain having a backside and a sidewall (Source drain 222 having a backside / curving-in side and a sidewall /vertical curving-out side-Examiner's annotated Fig 2);
a two-stage backside contact (Two-stage backside contact 224-Examiner's annotated Fig 2) having
an upper portion (Upper portion 224 as indicated by dashed line upper rectangle, contacting backside / curving-in side and a sidewall /vertical curving-out side of source drain 222-Examiner's annotated Fig 2) and
a lower portion (Lower portion 221 as indicated by dashed line lower rectangle, contacting Backside first metal line 220, and contacting upper portion 224 being a portion of the same structure 224-Examiner's annotated Fig 2),
wherein the upper portion contacts the backside of the source drain and at least part of the sidewall of the source drain (Upper portion 224 as indicated by dashed line upper rectangle, contacting backside / curving-in side and at least part of sidewall /vertical curving-out side of source drain 222-Examiner's annotated Fig 2); and
a backside first metal line (Backside first metal line 220-Examiner's annotated Fig 2);
wherein the lower portion contacts the upper portion and contacts the backside first metal line (Lower portion 221 as indicated by dashed line lower rectangle, contacting Backside first metal line 220, and contacting upper portion 224 being a portion of the same structure 224-Examiner's annotated Fig 2).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US20250054822A1-Ko22) in view of Su et al. (US 20210376076 A1-Su76).
Regarding claim 4, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 does not disclose a semiconductor structure
wherein the upper portion has a height that is less than a height of the lower portion.
Su76 teaches a semiconductor structure
wherein the upper portion has a height that is less than a height of the lower portion (Upper portion having a height being less than a height of the lower portion (Upper portion 136 having a height being less than a height of lower portion 138 as indicated by the vertical continuous lines-Examiner's annotated Fig 25A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Ko22, as taught by Su76 for the purpose of reducing contact resistance of the nano-FETs (Su76: [0082]).
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Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US20250054822A1-Ko22) in view of Ju et al. (US 20210351303 A1-Ju03).
Regarding claim 9, Ko22 discloses all the elements of claim 1, as noted above.
Ko22 does not disclose a semiconductor structure
wherein the upper portion and the lower portion are composed of the same material.
Ju03 teaches a semiconductor structure
wherein the upper portion and the lower portion are composed of the same material (Upper portion 120 and lower portion 122 being composed of metal materials such as tungsten so of the same material-[0027] L1-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Ko22, as taught by Ju03 for the purpose of reducing cell capacitance (Jo03: [0020]).
Claim(s) 11-12, 16, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do et al. (US 20210384106 A1-Do06) in view of Ju et al. (US 20210351303 A1-Ju03).
Regarding claim 11, Do06 discloses all the elements of claim 10, as noted above.
Do06 does not disclose a semiconductor structure
wherein the upper portion has a largest width that is less than a lower portion largest width largest width of the lower portion.
Ko22 teaches a semiconductor structure
wherein the upper portion has a largest width that is less than a largest width of the lower portion (Upper portion DBC having largest width being less than a largest width of lower portion MPR4 as indicated by continuous lines-Examiner's annotated Fig 9B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Ko22 for the purpose of minimizing overlay errors of patterns formed at different vertical levels (Ko22: [0004]).
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Regarding claim 12, Do06 discloses all the elements of claim 10, as noted above.
Do06 does not disclose a semiconductor structure
wherein the upper portion has a largest width that is less than a smallest width of the lower portion.
Ko22 further teaches a semiconductor structure
wherein the upper portion has a largest width that is less than a smallest width of the lower portion (Upper portion DBC having largest width being less than a smallest width of lower portion MPR4 as indicated by continuous lines-Examiner's annotated Fig 9B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Ko22 for the purpose of minimizing overlay errors of patterns formed at different vertical levels (Ko22: [0004]).
Regarding claim 16, Do06 discloses all the elements of claim 10, as noted above.
Do06 does not teach a semiconductor structure
wherein the upper portion is laterally centered with respect to the lower portion.
Ko22 further teaches a semiconductor structure
wherein the upper portion is laterally centered with respect to the lower portion (Upper portion VPR being laterally centered with respect to lower portion MPR as indicated by dashed lines-Examiner's annotated Fig 8C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Ko22 for the purpose of minimizing overlay errors of patterns formed at different vertical levels (Ko22: [0004]).
Regarding claim 19, Do06 discloses all the elements of claim 10, as noted above.
Do06 does not teach a semiconductor structure
a frontside interlevel dielectric,
wherein the upper portion is in the frontside interlevel dielectric.
Ko22 further teaches a semiconductor structure
a frontside interlevel dielectric (Frontside interlevel dielectric silicon oxide 112-Fig 9C, [0081] L1-11),
wherein the upper portion is in the frontside interlevel dielectric (Upper portion DBC in the frontside interlevel dielectric 112-Fig 9C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Ko22 for the purpose of minimizing overlay errors of patterns formed at different vertical levels (Ko22: [0004]).
Claim(s) 13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do et al. (US 20210384106 A1-Do06) in view of Su et al. (US 20210376076 A1-Su76).
Regarding claim 13, Do06 discloses all the elements of claim 10, as noted above.
Do06 does not disclose a semiconductor structure
wherein the upper portion has a height that is less than a height of the lower portion.
Su76 teaches a semiconductor structure
wherein the upper portion has a height that is less than a height of the lower portion (Upper portion having a height being less than a height of the lower portion (Upper portion 136 having a height being less than a height of lower portion 138 as indicated by the vertical continuous lines-Examiner's annotated Fig 25A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Su76 for the purpose of reducing contact resistance of the nano-FETs (Su76: [0082]).
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Regarding claim 18 , Do06 discloses all the elements of claim 10, as noted above.
Do06 does not disclose a semiconductor structure further comprising:
a frontside interlevel dielectric; and
a backside dielectric layer;
wherein the lower portion is partially in the frontside interlevel dielectric and
partially in the backside dielectric layer.
Su76 teaches a semiconductor structure further comprising:
a frontside interlevel dielectric (frontside interlevel dielectric 130-Fig 25A, [0081] L1-7); and
a backside dielectric layer (backside dielectric layer ILD 132-Fig 25A);
wherein the lower portion is partially in the frontside interlevel dielectric (Lower portion 138 being partially in the frontside interlevel dielectric 130-Fig 25A) and
partially in the backside dielectric layer (Lower portion 138 being partially in the backside interlevel dielectric 132-Fig 25A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Su76 for the purpose of reducing contact resistance of the nano-FETs (Su76: [0082]).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 14, over Do et al. (US 20210384106 A1-Do06) discloses all the elements of claim 10, as noted above.
Do06 further discloses a semiconductor structure
wherein the top source drain is a first top source drain (top source drain 26_U1 being a first top source drain-Fig 2B), and
further comprising a second top source drain having a backside (Second top source drain 26_U2 having a backside/ Bottom side-Fig 2B).
Do06 does not disclose a semiconductor structure
wherein the upper portion contacts the backside of the second top source drain.
Lanzillo et al. (US 20240421038 A1-Lanzillo38) teaches a semiconductor structure
wherein the upper portion contacts the backside of the second top source drain (upper portion 220a contacting the backside of the second top source drain 206b-Fig 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a method for forming a semiconductor structure of Do06, as taught by Lanzillo38 for the purpose of allowing for both the bottom and top devices to have power supplied from the backside thereby leaving more wiring resources for the frontside (Lanzillo38: [0030]).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it does not constitute prior art under 35 U.S.C. 102(a)(2).
References such as Do et al. (US 20210384106 A1-Do06), teaches a semiconductor structure but does not teach or suggest a semiconductor structure, namely “wherein the upper portion contacts the backside of the second top source drain”, in combination with other claimed elements.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hong et al. (US 20250185332 A1-Hong32) discloses a semiconductor structure comprising a first source drain (216a-Fig 2); a two-stage backside contact (214/207-Fig 2); and a backside first metal line (208-Fig 2).
Cheng et al. (US 20230187551 A1-Cheng 51) discloses a semiconductor structure comprising a bottom source drain (162-1 in Fig 1); a top source drain located above the bottom source drain (160-1 above 162-1), a two-stage backside contact ( upper and lower portions of 191); and a backside first metal line (200).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/30/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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