DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species A, fig. 11, claims 1, 3-5, 7-12, 14-20, in the reply filed on 7/15/26 is acknowledged.
Claims 2, 6, 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/15/26.
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 11, 12, 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4, 7, 8 and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chun et al., KR 20050069591 A (see attached English machine translation).
Chun anticipates:
A semiconductor device comprising (see fig. 2)
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354
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: an interconnection (210) disposed on a substrate;
an interlayer insulating layer (231/232) disposed on the interconnection;
a capping layer (233) disposed on the interlayer insulating layer;
a conductive bonding pattern (e.g. upper, wide 260) disposed in a pad trench (e.g. pad trench annotated in fig. 2) which passes through the capping layer and extends into the interlayer insulating layer;
a spacer (310 or 320 or 310+320) disposed in the pad trench, and contacting a side surface of the conductive bonding pattern (e.g. upper, wide 260); and
a contact plug (e.g. lower, narrow 260) disposed in a contact hole (e.g. contact hole annotated in fig. 2) which passes through the interlayer insulating layer and is aligned with a center of the pad trench,
wherein the contact plug (e.g. lower, narrow 260) contacts the interconnection (210), and
wherein the conductive bonding pattern (e.g. upper, wide 260) is continuous to the contact plug (e.g. lower, narrow 260). See Chun at English machine translation pages 1-9, figs. 1-5.
3. The semiconductor device according to claim 1, wherein the spacer (310 or 320 or 310+320) comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride (SiCN), polysilicon, metal, metal oxide, metal nitride, metal silicate, or a combination thereof (e.g. USG comprises silicon oxide. See Chun at pages 4-5.)
4. The semiconductor device according to claim 1, wherein:
the spacer comprises silicon oxide (e.g. USG comprises silicon oxide. See Chun at pages 4-5.); and
an uppermost end of the spacer is disposed at a lower level than an uppermost end of the interlayer insulating layer (e.g. When the spacer is interpreted to be 320 in claim 1, then an uppermost end is lower than an uppermost end of the interlayer insulating layer 231/232.)
7. The semiconductor device according to claim 1, wherein the spacer (310 or 320 or 310+320) surrounds a side surface of the conductive bonding pattern (e.g. upper, wide 260), fig. 2.
8. The semiconductor device according to claim 1, wherein the contact plug (e.g. lower, narrow 260) is aligned according to a profile of the spacer (310 or 320 or 310+320), fig. 2
10. The semiconductor device according to claim 1, further comprising an etch stop layer (220) disposed between the interconnection (210) and the interlayer insulating layer (231/232),
wherein the contact plug (e.g. lower, narrow 260) contacts the interconnection (210) by passing through the etch stop layer (220), fig. 2.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun as applied to claim 1 above.
Regarding claim 5:
Chun is silent a vertical distance between a lower surface of the capping layer and an uppermost end of the spacer is about 10 nm to 50 nm.
However, Chun teaches in fig. 4, the thickness of the spacer forming layer (300) is 300 angstroms = 30 nm at page 5. Thus, the distance between a lower surface of the capping layer and an uppermost end of the spacer is at least 30 nm.
It would have been obvious to one of ordinary skill in the art to form “wherein a vertical distance between a lower surface of the capping layer (233) and an uppermost end of the spacer (320) is about 10 nm to 50 nm” because in Chun’s fig. 4 the distance between a lower surface of the capping layer and an uppermost end of the spacer is at least 30 nm.
Furthermore, absent any disclosure by the Applicant that a distance of 10 nm to 50 nm is critical or provides for unexpected results, such a distance can be considered within the skill level of one of ordinary skill in the art or by the guidance provided by Chun.
See MPEP § 2144.05, Obviousness of Ranges:
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
Smith v. Nichols, 88 U.S. 112, 118-19 (1874) (a change in form, proportions, or degree "will not sustain a patent").
[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Regarding claim 9:
Chun further teaches:
. 9. The semiconductor device according to claim 1, wherein:
the interlayer insulating layer (232/233) comprises silicon oxide (e.g. USG comprises silicon oxide. See Chun at pages 4-5.)
Chun does not expressly teach:
the capping layer comprises silicon carbonitride (SiCN), silicon nitride, or a combination thereof.
However, it would have been obvious to one having ordinary skill in the art to form “the capping layer comprises silicon carbonitride (SiCN), silicon nitride, or a combination thereof”, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al., US Publication No. 2023/0138478 A1 in view of Chun et al., KR 20050069591 A (see attached English machine translation).
Choi teaches:
16. A semiconductor device comprising (see figs. 14-15):
a first structure (PERI); and
a second structure (CELL) bonded onto the first structure,
wherein the first structure (PERI) comprises
a first integrated circuit (120);
a first interconnection (182) disposed on the first integrated circuit;
a first interlayer insulating layer (190) disposed on the first interconnection;
a first capping layer (186) disposed on the first interlayer insulating layer;
a first conductive bonding pattern (184) disposed in a first pad trench which passes through the first capping layer (186) and extends into the first interlayer insulating layer (190); and
a first contact plug (182) disposed in a first contact hole which passes through the first interlayer insulating layer and is aligned with a center of the first pad trench,
wherein the first contact plug (182) contacts the first interconnection (182),… See Chen at para. [0111] – [0119].
Choi does not expressly teach:
a first spacer disposed in the first pad trench, and contacting a side surface of the first conductive bonding pattern; and
wherein the first conductive bonding pattern is continuous to the first contact plug.
In an analogous art, Chun teaches these limitations as applied to claim 1 above.
It would have been obvious to a person of ordinary skill in the art to modify Choi’s conductive structure (180) with Chun’s conductive structure (230) to prevent “peeling phenomenon” and exposure to air. See Chun at page 2. Also see Chun’s’ disclosure of first to fourth advantages in the “Advantageous Effects” section at page 6.
Regarding claim 17:
Choi further teaches:
17. The semiconductor device according to claim 16, wherein the second structure comprises (CELL):
a second integrated circuit (245);
a second interconnection (280) disposed on the second integrated circuit;
a second interlayer insulating layer (290) disposed on the second interconnection;
a second capping layer (286) disposed on the second interlayer insulating layer;
a second conductive bonding pattern (284) disposed in a second pad trench; and
a second contact plug (282) disposed in a second contact hole which passes through the second interlayer insulating layer and is aligned with a center of the second pad trench,
wherein the second capping layer (286) faces the first capping layer (186), and
wherein the second conductive bonding pattern (284) is bonded onto the first conductive bonding pattern (184), figs. 14-15.
Choi does not expressly teach:
a second spacer disposed in the second pad trench, and contacting a side surface of the second conductive bonding pattern; and
Chun teaches these limitations as applied to claim 1 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Choi with the teachings of Chun because (i) the adhesion problem does not occur; (ii) it is advantageous to secure margins by increasing the CD (Critical Dimension); (Iii) sufficient step coverage margin can be ensured; and (iv) air exposure can be prevented. See Chun at “Advantageous Effects” section at page 6.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
10 September 2026
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