Prosecution Insights
Last updated: October 02, 2026
Application No. 18/623,193

EMBEDDED MAGNETIC DEVICE INTEGRATED STRUCTURE AND MANUFACTURING METHOD THEREOF

Non-Final OA §103
Filed
Apr 01, 2024
Priority
Mar 31, 2023 — CN 2023103489979
Examiner
ROBERTSON, NOAH CHRISTOPHER
Art Unit
Tech Center
Assignee
ZHUHAI ACCESS SEMICONDUCTOR CO., LTD.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-60.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
26 currently pending
Career history
9
Total Applications
across all art units
This examiner has no resolved cases yet (career too new); statute-level performance unavailable. The Grant Probability card shows Tech Center averages instead.

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group II (e.g., Claims 8-15) in the reply filed on July 21st, 2026, is acknowledged. Therefore, the restriction/election requirement dated May 22nd, 2026, is hereby made FINAL. Status of Claims Pursuant to Applicant’s reply to restriction/election requirement filed July 21st, 2026, Claims 1-7 are withdrawn as being drawn to a non-elected invention and Claims 8-15 are pending the within examination. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. More specifically, Applicant’s priority request to CN 2023103489979 with a filing date of March 31st, 2023, is acknowledged. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Information Disclosure Statement No information disclosure statement (IDS) has been provided by Applicant prior to the within examination. Drawings The drawings are objected to because the unlabeled rectangular boxes shown in the drawings should be provided with descriptive labels. As an example, Fig. 1B adds new features to the drawings in comparison to Fig. 1A, but said new features are not provided with a label. Likewise, Fig. 1C adds new features in the manufacturing process compared to Fig. 1B, but said new features are not provided with a label. In total, this is the case for Figs. 1B, 1C, 1D, 1E, 1G, 1M, and 1O. Appropriate correction is required. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The specification is objected to as the section headings are in bold type. Pursuant to MPEP 608.01(a) and 37 C.F.R. 1.77(c), “The text of the specification sections defined in paragraphs (b)(1) through (b)(12) of this section, if applicable, should be preceded by a section heading in uppercase and without underlining or bold type” (emphasis added). The instant application has section headings with bold type. Appropriate correction is required. The specification is objected to as failing to follow 37 C.F.R. 1.74 and MPEP 608.01(f). More specifically, the Brief Description of Drawings section of the specification is objected to because the drawings show Figures 1A, 1B, 1C, etc., but the brief description provided on page 3, lines 27-29, does not provide a brief description for each individual figure (e.g., a separate description for Fig. 1A, for Fig. 1B, for Fig. 1C, etc.) as is stated in MPEP 608.01(f). Appropriate correction is required. Claim Objections Claim 8 is objected to because of the following informalities: a) in step (e), “… the embedded element” should read “an embedded element” to avoid antecedent basis issues. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 8 and 10-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, et al. (CN 113053849 A; hereinafter referred to as Chen) and further in view of Miyazaki, et al. (US 20130200977 A1; hereinafter referred to as Miyazaki). PNG media_image1.png 640 1320 media_image1.png Greyscale Regarding Claim 8, Chen discloses a manufacturing method of an embedded magnetic device integrated structure, the method comprising: (a) providing a bearing board (temporary bearing plate, [0071], Fig. 5a); (b) forming a coil, an electrode on the coil, a first conducting post (first conductive copper pillar 130a, [0071], Fig. 5b), and a sacrificial metal block (sacrificial cooper pillars 180a, [0071], Fig. 5b) on the bearing board (Fig. 5b), wherein the coil extends parallel to the bearing board and the electrode extends perpendicular to the coil (); (c) laminating a sheet-like magnetic material (first magnetic layer 150a, [0075], Fig. 5a) and an insulating material ([0081], Fig. 5c) to form a first magnetic layer covering the coil (first magnetic core 141a, [0075], Fig. 5b) and a second insulating layer covering the first magnetic layer (first core dielectric layer, [0081], Fig. 5c); wherein the coil and the electrode are embedded in the second insulating layer (Fig. 5c); (d) thinning the second insulating layer to expose the electrode, the first conducting post and the sacrificial metal block ([0081], Fig. 5c); (e) removing the bearing board ([0082], Fig. 5d) and etching the exposed sacrificial metal block to form a cavity for the embedded element (opening 110, [0098], Fig. 2); (f) forming an adhesive layer on a surface of the second insulating layer exposing the coil (adhesive layer, [0101]), placing an element in the cavity (device, [0102]), and fixing a terminal of the element via the adhesive layer (Fig. 4); (g) laminating a sheet-like magnetic material and an insulating material on the surface of the second insulating layer exposing the first magnetic layer to form a second magnetic layer on the first magnetic layer (second magnetic core 141b, [0083], Fig. 5e) and a third insulating layer on the second magnetic layer (second core dielectric layer, [0091], Fig. 5f); (h) removing the adhesive layer ([0103]); and (i) forming a first wiring layer on the surface of the second insulating layer (first circuit layer 310, [0106], Fig. 4), and forming a second wiring layer on the surface of the third insulating layer ([second] wiring layer, [0106], annotated Fig. 4); wherein the first conducting post is used for conductively connecting the first wiring layer and the second wiring layer ([0106]). Chen fails to explicitly disclose the forming of a coil, an electrode on the coil, and wherein the coil extends parallel to the bearing board and the electrode extends perpendicular to the coil, as Chen more broadly discloses a magnetic core/layer and does not state the formation of coils or electrodes or their positional relationship. However, in analogous art, Miyazaki discloses forming a coil (planar coils 110, [0049], Figs. 2, 4a), an electrode on the coil (terminal electrode 114, [0049], Fig. 2), and wherein the coil extends parallel to the bearing board and the electrode extends perpendicular to the coil (Fig. 2; the planar coils are planar extending parallel to the substrate while the terminal electrode extends in a vertical direction perpendicular to the substrate). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the inductor structure as disclosed by Chen such that a coil is formed, an electrode is formed on the coil, and that said coil and electrode are extending as disclosed by Miyazaki. One would be motivated to do so as a structure in such a manner eliminates the possibility of a defective inductor element and prevents the finished inductor quality from affecting the substrate yield (Miyazaki: [0066]). Regarding Claim 10, Chen/Miyazaki discloses the manufacturing method according to claim 8, wherein at least two electrodes are connected to the coil (Miyazaki: Fig. 2). Regarding Claim 11, Chen/Miyazaki discloses the manufacturing method according to claim 8, wherein the second insulating layer is made from a glass fiber-containing resin material (Chen: [0009]). Regarding Claim 12, Chen/Miyazaki discloses the manufacturing method according to claim 8, wherein the bearing board comprises a first metal layer (Chen: first copper foil 210, [0072], Fig. 5a) and a second metal layer laminated (Chen: second copper foil 220, [0072], Fig. 5a); and the step (e) comprises: (e1) forming a third photoresist layer on the second insulating layer (Chen: third photoresist layer 160e, Fig. 5g); (e2) separating the first metal layer and the second metal layer (Chen: [0082]); and (e3) etching a metal layer attached to the second insulating layer to expose the coil, the electrode, the first conducting post, the sacrificial metal block, the first magnetic layer and the second insulating layer (Chen: Fig. 5e). Regarding Claim 13, Chen/Miyazaki discloses the manufacturing method according to claim 8, wherein the third insulating layer is made from a glass fiber-free resin material (Chen: [0009]). Regarding Claim 14, Chen/Miyazaki discloses the manufacturing method according to claim 8, further comprising: (j1) laminating a fourth insulating layer on the first wiring layer and the second wiring layer, respectively (Chen: see Annotated Fig. 4); (j2) forming a second conducting post penetrating the fourth insulating layer (Chen: see Annotated Fig. 4); and (j3) forming a third wiring layer respectively on both surfaces of the fourth insulating layer (Chen: [third] wiring layer 320, [0065], see Annotated Fig. 4), wherein the third wiring layer respectively conductively connects to the first wiring layer and the second wiring layer through the second conducting posts (Chen: [0065], see Annotated Fig. 4). Regarding Claim 15, Chen/Miyazaki discloses the manufacturing method according to claim 14, further comprising: (k) forming a solder mask on the third wiring layer (Chen: solder resist layer 340, [0067], Fig. 4), and exposing the third wiring layer through a solder mask opening (Chen: solder resist layer opening 350, [0067], Fig. 4). Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen/Miyazaki as applied to claims 8 and 10-15 above, and further in view of Fujii (US 20130271252 A1; hereinafter referred to as Fujii). Regarding Claim 9, Chen/Miyazaki discloses the manufacturing method according to claim 8, and the step (b) comprises: (b1) forming a first photoresist layer comprising a first pattern (Chen: photoresist layer 160a, [0079], Fig. 5b); (b2) electroplating the first pattern to form the coil and part of the electrode, part of the first conducting post and part of the sacrificial metal block (Chen: [0079]); (b3) forming a second photoresist layer comprising a second pattern on the first photoresist layer (Chen: photoresist layer 160b, [0078-0080], Fig. 5b); (b4) electroplating the second pattern to form the electrode, the first conducting post, and the sacrificial metal block (Chen: [0079]); and (b5) removing the first photoresist layer and the second photoresist layer (Chen: [0080], Fig. 5c). The combination of Chen/Miyazaki fails to disclose that the bearing board further comprises a first seed layer and a first photo resist layer comprising a first pattern being formed on the first seed layer. However, in analogous art, Fujii discloses a bearing board further comprising a first seed layer (seed layer 153c, [0146], Fig. 5A), and forming a first photoresist layer comprising a first pattern (Fujii: mask 301, [0148], Fig. 5B) on the first seed layer (Fig. 5B; the mask 301 is formed on the first seed layer 153c). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the bearing board as disclosed by Chen/Miyazaki to include a seed layer as disclosed by Fujii, and that the first photoresist layer of Chen/Miyazaki would be placed on the seed layer of Fujii. One would be motivated to do so because the inclusion of a seed layer leads to more efficient formation of coil structures as the seed layer can be used to feed power to the device (Fujii: [0149]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. a) Aoki, et al. (US 20180374803 A1); discloses a wiring substrate b) Morita, et al. (US 20200315034 A1); discloses a device-embedded board and method for manufacturing the same c) Mano, et al. (US 20120212919 A1); discloses an inductor component and printed wiring board Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000. /Noah C. Robertson/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Apr 01, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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